📄 wrsbc85xx.h
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#define M85XX_SVR(base) (CAST(VUINT32 *)((base) + 0xE00A4))#define _PPC_BUCSR_FI 0x200 /* Invalidate branch cache */#define _PPC_BUCSR_E 0x1 /* Enable branch prediction *//* Serial port settings and offsets */#define N_SIO_CHANNELS 2#define N_UART_CHANNELS N_SIO_CHANNELS#define UART_REG_INTVL 1#define DEFAULT_BAUD_RATE 9600/* 8540 */#define XTAL_CHIP sysClkFreqGet()#define COM1_CCSR_OFFSET 0x4500#define COM2_CCSR_OFFSET 0x4600#define COM1_CHIP_ADRS ((ULONG) CCSBAR + (ULONG) COM1_CCSR_OFFSET)#define COM2_CHIP_ADRS ((ULONG) CCSBAR + (ULONG) COM2_CCSR_OFFSET)/* 8560 */#define XTAL_BRD 1843200#define NS16550_BASE_ADRS UTIL_DUART1#define COM1_BRD_ADRS NS16550_BASE_ADRS#define COM1_INT_VEC 9#define COM1_INT_LVL COM1_INT_VEC#define COM2_ADRS_OFFSET 0x100000#define COM2_BRD_ADRS (NS16550_BASE_ADRS + COM2_ADRS_OFFSET)#define COM2_INT_VEC 10 #define COM2_INT_LVL COM2_INT_VEC/* 7 segment LED */#define LED_DISP_OFF 0xff#define LED_DISP_DOT 0xfe#define LED_DISP_A 0x11#define LED_DISP_B 0x01#define LED_DISP_C 0x63#define LED_DISP_D 0x03#define LED_DISP_E 0x61#define LED_DISP_F 0x71#define LED_DISP_0 (LED_DISP_D & LED_DISP_DOT)#define LED_DISP_1 (~0x60 & LED_DISP_DOT)#define LED_DISP_2 (~0xda & LED_DISP_DOT)#define LED_DISP_3 (0x0d & LED_DISP_DOT)#define LED_DISP_4 (0x99 & LED_DISP_DOT)#define LED_DISP_5 (0x49 & LED_DISP_DOT)#define LED_DISP_6 (0x41 & LED_DISP_DOT)#define LED_DISP_7 (~0xe0 & LED_DISP_DOT)#define LED_DISP_8 (LED_DISP_B & LED_DISP_DOT)#define LED_DISP_9 (0x09 & LED_DISP_DOT)/* Clock rates */#define SYS_CLK_RATE_MIN 1 /* minimum system clock rate */#define SYS_CLK_RATE_MAX 8000 /* maximum system clock rate */#define AUX_CLK_RATE_MIN 7 /* minimum auxiliary clock rate */#define AUX_CLK_RATE_MAX 32552 /* maximum auxiliary clock rate */#define WDT_RATE_MIN (sysTimerClkFreq / (1 << 29))#define WDT_RATE_MAX (sysTimerClkFreq / (1 << 21))/* Maximum number of SCC channels to configure as SIOs. Note that this * assumes sequential usage of SCCs. SCC serial not used in wrSbc85xx. */#define MAX_SCC_SIO_CHANS 2#define M85XX_CPM_SICR(base) (CAST(VUINT16 *)((base) + 0x90c00))#define M85XX_CPM_SIVEC(base) (CAST(VUINT8 *)((base) + 0x90c04))#define M85XX_CPM_SIPNR_H(base) (CAST(VUINT32 *)((base) + 0x90c08))#define M85XX_CPM_SIPNR_L(base) (CAST(VUINT32 *)((base) + 0x90c0c))#define M85XX_CPM_SCPRR_H(base) (CAST(VUINT32 *)((base) + 0x90c14))#define M85XX_CPM_SCPRR_L(base) (CAST(VUINT32 *)((base) + 0x90c18))#define M85XX_CPM_SIMR_H(base) (CAST(VUINT32 *)((base) + 0x90c1c))#define M85XX_CPM_SIMR_L(base) (CAST(VUINT32 *)((base) + 0x90c20))#define M85XX_CPM_SIEXR(base) (CAST(VUINT32 *)((base) + 0x90c24))#define M85XX_CPM_SCCR(base) (CAST(VUINT32 *)((base) + 0x90c80))/* PCI defines and access macros */#define CCSR_PCI_OFFSET 0x08000#define PCI_REGBASE (CCSBAR | CCSR_PCI_OFFSET)#define PCI_CLK_FREQ 1843200#define PCI_MEMIO2LOCAL(x) \ (((UINT32)x - PCI_MEMIO_ADRS) + CPU_PCI_MEMIO_ADRS) /* PCI IO memory adrs to CPU bus adrs */ #define PCI_IO2LOCAL(x) \ (((UINT32)x - PCI_IO_ADRS) + CPU_PCI_IO_ADRS) #define PCI_MEM2LOCAL(x) \ (((UINT32)x - PCI_MEM_ADRS) + CPU_PCI_MEM_ADRS)/* CPU bus adrs to PCI (non-prefetchable) memory address */ #define LOCAL2PCI_MEMIO(x) \ ((int)(x) + PCI_MSTR_MEM_BUS)#define PCI_CFG_ADR_REG (CCSBAR + 0x8000)#define PCI_CFG_DATA_REG (CCSBAR + 0x8004)#define PCI_AUTO_CONFIG_ADRS 0x4c00#define PPCACR_PRKM_MASK 0XF0#define PCI_REQUEST_LEVEL 0x3#define CLASS_OFFSET 0xB#define CLASS_WIDTH 0x1#define BRIDGE_CLASS_TYPE 0x6#define PCICMD_ADRS (PCI_CFG_BASE + 0x04) /* PCI cmd reg */#define PCICMD_VAL 0x00000006 /* PCI COMMAND Default value */#define PCISTAT_ADRS (PCI_CFG_BASE + 0x06) /* PCI status reg */#define NUM_PCI_SLOTS 0x5 /* 5 PCI slots: 0 to 4 - sebf */#define PCI_INTA_IRQ 0x2 /* PCI INTA routed to IRQ2 */#define PCI_INTB_IRQ 0x3 /* PCI INTB routed to IRQ3 */#define PCI_INTC_IRQ 0x4 /* PCI INTC routed to IRQ4 */#define PCI_INTD_IRQ 0x5 /* PCI INTD routed to IRQ5 */#define PCI_SLOT1_DEVNO 0x10 /* PCI SLOT 1 Device no */#define PCI_LAT_TIMER 0x40 /* latency timer value, 64 PCI clocks */#define PCI1_DEV_ID 0x826010E3#define PCI2_DEV_ID 0x826110E3#define PCI3_DEV_ID 0x826210E3#define PCI_DEV_ID_82XX 0x00031057 /* Id for MPC85xx - Rev1 */#define PCI_DEV_ID_85XX 0x00091057 /* Id for MPC85xx - Rev2 */#define PCI_ID_I82559 0x12298086 /* Id for Intel 82559 */#define PCI_ID_I82559ER 0x12098086 /* Id for Intel 82559 ER */#define MPC8266ADS_PCI_IRQ 08#define PCI_XINT1_LVL PCI_INTA_IRQ#define PCI_XINT2_LVL PCI_INTB_IRQ#define PCI_XINT3_LVL PCI_INTC_IRQ#define PCI_XINT4_LVL PCI_INTD_IRQ#define PMC1_DEVNO 0x13 /* device number of the PCI-PMC slot (slot 0) */#define PMC1_PCI_DRV PCI_INTA_IRQ /* default interrupt line, unused */#define PMC2_PCI_DRV PMC1_PCI_DRV /* no PCI-PMC secondary slot on wrSbc8560 */#define PCI_MSTR_MEMIO_LOCAL PCI_MEMIO_ADRS/* specific MPC8560 additional pci/x config header registers */#define PCI_CFG_PBFR 0x44#define PCI_CFG_PBACR 0x46#define PCI_CFG_PXNCIR 0x60#define PCI_CFG_PXCPR 0x61#define PCI_CFG_PXCR 0x62#define PCI_CFG_PXSR 0x64#ifndef _ASMLANGUAGE#ifndef PCI_IN_BYTE#define PCI_IN_BYTE(x) sysPciInByte (x)IMPORT UINT8 sysPciInByte (UINT32 address);#endif#ifndef PCI_IN_WORD#define PCI_IN_WORD(x) sysPciInWord (x)IMPORT UINT16 sysPciInWord (UINT32 address);#endif#ifndef PCI_IN_LONG#define PCI_IN_LONG(x) sysPciInLong (x)IMPORT UINT32 sysPciInLong (UINT32 address);#endif#ifndef PCI_OUT_BYTE#define PCI_OUT_BYTE(x,y) sysPciOutByte (x,y)IMPORT void sysPciOutByte (UINT32 address, UINT8 data);#endif#ifndef PCI_OUT_WORD#define PCI_OUT_WORD(x,y) sysPciOutWord (x,y)IMPORT void sysPciOutWord (UINT32 address, UINT16 data);#endif#ifndef PCI_OUT_LONG#define PCI_OUT_LONG(x,y) sysPciOutLong (x,y)IMPORT void sysPciOutLong (UINT32 address, UINT32 data);#endif#endif /* _ASMLANGUAGE */#define DELTA(a,b) (abs((int)a - (int)b))#define BUS 0 /* bus-less board *//* This value is the setting for the MPTPR[PTP] Refresh timer prescaler. * The value is dependent on the OSCILLATOR_FREQ value. For other values * a conditionally compiled term must be created here for that OSCILLATOR_FREQ * value. * * BRGCLK_DIV_FACTOR * Baud Rate Generator division factor - 0 for division by 1 * 1 for division by 4 * 2 for division by 16 * 3 for division by 64 */#define DIV_FACT_4 0#define DIV_FACT_16 1#define DIV_FACT_64 2#define DIV_FACT_256 3#if (OSCILLATOR_FREQ == FREQ_66_MHZ)# define TPR 0x2000# define BRGCLK_DIV_FACTOR DIV_FACT_16#endif#define M8260_BRGC_DIVISOR BRGCLK_DIV_FACTOR/* Port A, B, C and D Defines */#define PA31 (0x00000001)#define PA30 (0x00000002)#define PA29 (0x00000004)#define PA28 (0x00000008)#define PA27 (0x00000010)#define PA26 (0x00000020)#define PA25 (0x00000040)#define PA24 (0x00000080)#define PA23 (0x00000100)#define PA22 (0x00000200)#define PA21 (0x00000400)#define PA20 (0x00000800)#define PA19 (0x00001000)#define PA18 (0x00002000)#define PA17 (0x00004000)#define PA16 (0x00008000)#define PA15 (0x00010000)#define PA14 (0x00020000)#define PA13 (0x00040000)#define PA12 (0x00080000)#define PA11 (0x00100000)#define PA10 (0x00200000)#define PA9 (0x00400000)#define PA8 (0x00800000)#define PA7 (0x01000000)#define PA6 (0x02000000)#define PA5 (0x04000000)#define PA4 (0x08000000)#define PA3 (0x10000000)#define PA2 (0x20000000)#define PA1 (0x40000000)#define PA0 (0x80000000)#define PB31 (0x00000001)#define PB30 (0x00000002)#define PB29 (0x00000004)#define PB28 (0x00000008)#define PB27 (0x00000010)#define PB26 (0x00000020)#define PB25 (0x00000040)#define PB24 (0x00000080)#define PB23 (0x00000100)#define PB22 (0x00000200)#define PB21 (0x00000400)#define PB20 (0x00000800)#define PB19 (0x00001000)#define PB18 (0x00002000)#define PB17 (0x00004000)#define PB16 (0x00008000)#define PB15 (0x00010000)#define PB14 (0x00020000)#define PB13 (0x00040000)#define PB12 (0x00080000)#define PB11 (0x00100000)#define PB10 (0x00200000)#define PB9 (0x00400000)#define PB8 (0x00800000)#define PB7 (0x01000000)#define PB6 (0x02000000)#define PB5 (0x04000000)#define PB4 (0x08000000)#define PC31 (0x00000001)#define PC30 (0x00000002)#define PC29 (0x00000004)#define PC28 (0x00000008)#define PC27 (0x00000010)#define PC26 (0x00000020)#define PC25 (0x00000040)#define PC24 (0x00000080)#define PC23 (0x00000100)#define PC22 (0x00000200)#define PC21 (0x00000400)#define PC20 (0x00000800)#define PC19 (0x00001000)#define PC18 (0x00002000)#define PC17 (0x00004000)#define PC16 (0x00008000)#define PC15 (0x00010000)#define PC14 (0x00020000)#define PC13 (0x00040000)#define PC12 (0x00080000)#define PC11 (0x00100000)#define PC10 (0x00200000)#define PC9 (0x00400000)#define PC8 (0x00800000)#define PC7 (0x01000000)#define PC6 (0x02000000)#define PC5 (0x04000000)#define PC4 (0x08000000)#define PC3 (0x10000000)#define PC2 (0x20000000)#define PC1 (0x40000000)#define PC0 (0x80000000)#define PD31 (0x00000001)#define PD30 (0x00000002)#define PD29 (0x00000004)#define PD28 (0x00000008)#define PD27 (0x00000010)#define PD26 (0x00000020)#define PD25 (0x00000040)#define PD24 (0x00000080)#define PD23 (0x00000100)#define PD22 (0x00000200)#define PD21 (0x00000400)#define PD20 (0x00000800)#define PD19 (0x00001000)#define PD18 (0x00002000)#define PD17 (0x00004000)#define PD16 (0x00008000)#define PD15 (0x00010000)#define PD14 (0x00020000)#define PD13 (0x00040000)#define PD12 (0x00080000)#define PD11 (0x00100000)#define PD10 (0x00200000)#define PD9 (0x00400000)#define PD8 (0x00800000)#define PD7 (0x01000000)#define PD6 (0x02000000)#define PD5 (0x04000000)#define PD4 (0x08000000)#ifdef __cplusplus }#endif /* __cplusplus */#endif /* INCwrSbc85xxh */⌨️ 快捷键说明
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