wrsbc85xx.h

MPC8560 for vxwork BSP

/* wrSbc85xx.h - Wind River SBC 85xx board header */

/* Copyright 2002-2003 Wind River Systems, Inc. */

/*
modification history
--------------------
01s,30jul06,tor  Merge PCI support, cleanup
01r,09jun04,mil  Added VIRT_ADDR/PHYS_ADDR types conditionally.
01q,05may04,mil  Added LBCDLLSR and DDR defines and PCI ID for rev2 chips.
01p,02feb04,mil  Fixed redefine error for GNU Windows build.
01o,23oct03,mil  Cleanup.
01n,23oct03,mil  Added defines for 8560 COM2.
01m,12sep03,mil  Added defines for 8540 internal DUART.
01l,07jul03,mil  Added offsets for SCC regs.
01k,08jul02,dtr  Adding some PCI defines and macros.
*/

/* This file contains I/O addresses and related constants for the
 * Wind River SBC 85XX board. 
 */

#ifndef	INCwrSbc85xxh
#define	INCwrSbc85xxh

#ifdef	__cplusplus
    extern "C" {
#endif	/* __cplusplus */

#ifndef  _ASMLANGUAGE
# if (defined(_WRS_VXWORKS_MAJOR) && (_WRS_VXWORKS_MAJOR >= 6))
/* nothing needed */
# else  /* _WRS_VXWORKS_MAJOR */
typedef void * VIRT_ADDR;
typedef void * PHYS_ADDR;
# endif  /* _WRS_VXWORKS_MAJOR */
#endif  /* _ASMLANGUAGE */


#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS

#ifdef  _ASMLANGUAGE
#   define	CAST(x)
#else	/* _ASMLANGUAGE */
#   define	CAST(x)	(x)
typedef	volatile UCHAR	VCHAR;
typedef	volatile INT32	VINT32;
typedef	volatile INT16	VINT16;
typedef	volatile INT8	VINT8;
typedef	volatile UINT32	VUINT32;
typedef	volatile UINT16	VUINT16;
typedef	volatile UINT8	VUINT8;
#endif	/* _ASMLANGUAGE */

#endif /* M8260ABBREVIATIONS */

#ifndef EIEIO_SYNC
#   define EIEIO_SYNC  _WRS_ASM (" eieio; sync")
#endif        /* EIEIO_SYNC */
#ifndef EIEIO
#   define EIEIO    _WRS_ASM (" eieio")
#endif        /* EIEIO */

#define INIT_SKIP_PID2	1


/* Base address of CCSRBAR */

#define	CCSBAR		0xFE000000	/* CCSRBAR runtime value */
#define	CCSBAR_RST	0xFF700000	/* CCSRBAR reset value */
#define	IVPR_VAL	0x0		/* vector location */


/* Local access window offsets */

#define	M85XX_LAWBAR0(base)	(CAST(VUINT32 *)((base) + 0xc08))
#define	M85XX_LAWAR0(base)	(CAST(VUINT32 *)((base) + 0xc10))    
#define	M85XX_LAWBAR1(base)	(CAST(VUINT32 *)((base) + 0xc28))
#define	M85XX_LAWAR1(base)	(CAST(VUINT32 *)((base) + 0xc30))
#define	M85XX_LAWBAR2(base)	(CAST(VUINT32 *)((base) + 0xc48))
#define	M85XX_LAWAR2(base)	(CAST(VUINT32 *)((base) + 0xc50))
#define	M85XX_LAWBAR3(base)	(CAST(VUINT32 *)((base) + 0xc68))
#define	M85XX_LAWAR3(base)	(CAST(VUINT32 *)((base) + 0xc70))
#define	M85XX_LAWBAR4(base)	(CAST(VUINT32 *)((base) + 0xc88))
#define	M85XX_LAWAR4(base)	(CAST(VUINT32 *)((base) + 0xc90))
#define	M85XX_LAWBAR5(base)	(CAST(VUINT32 *)((base) + 0xcA8))
#define	M85XX_LAWAR5(base)	(CAST(VUINT32 *)((base) + 0xcB0))
#define	M85XX_LAWBAR6(base)	(CAST(VUINT32 *)((base) + 0xcc8))
#define	M85XX_LAWAR6(base)	(CAST(VUINT32 *)((base) + 0xcd0))
#define	M85XX_LAWBAR7(base)	(CAST(VUINT32 *)((base) + 0xce8))
#define	M85XX_LAWAR7(base)	(CAST(VUINT32 *)((base) + 0xcf0))

#define	LAWBAR_ADRS_SHIFT	12
#define	LAWAR_ENABLE		0x80000000
#define	LAWAR_TGTIF_PCI		0x00000000
#define	LAWAR_TGTIF_LBC		0x00400000
#define	LAWAR_TGTIF_RAPIDIO	0x00c00000
#define	LAWAR_TGTIF_DDRSDRAM	0x00F00000

#define	LAWAR_SIZE_4KB		0x0000000B
#define	LAWAR_SIZE_8KB		0x0000000C
#define	LAWAR_SIZE_16KB		0x0000000D
#define	LAWAR_SIZE_32KB		0x0000000E
#define	LAWAR_SIZE_64KB		0x0000000F
#define	LAWAR_SIZE_128KB	0x00000010
#define	LAWAR_SIZE_256KB	0x00000011
#define	LAWAR_SIZE_512KB	0x00000012
#define	LAWAR_SIZE_1MB		0x00000013
#define	LAWAR_SIZE_2MB		0x00000014
#define	LAWAR_SIZE_4MB		0x00000015
#define	LAWAR_SIZE_8MB		0x00000016
#define	LAWAR_SIZE_16MB		0x00000017
#define	LAWAR_SIZE_32MB		0x00000018
#define	LAWAR_SIZE_64MB		0x00000019
#define	LAWAR_SIZE_128MB	0x0000001A
#define	LAWAR_SIZE_256MB	0x0000001B
#define	LAWAR_SIZE_512MB	0x0000001C
#define	LAWAR_SIZE_1GB		0x0000001D
#define	LAWAR_SIZE_2GB		0x0000001E


/* Local Bus Controller (LBC) Registers
 *
 * BRx 0-16 Base Address
 *     17-18 Extended Base Address 
 *     19-20 Port Size - 00 reserved
 *                     - 01 8bit
 *                     - 10 16bit
 *                     - 11 32bit
 *     21-22 Data Error Correction
 *                     - 00 reserved
 *                     - 01 Normal parity 
 *                     - 10 RMW parity generation (32-bit)
 *                     - 11 reserved
 *     23    Write Protect
 *     24-26 Machine Select = 000 GPCM
 *                          - 001->010 reserved
 *                          - 011 SDRAM
 *                          - 100->110 UPMA->UPMC
 *                          - 111 reserved
 *     28-29 Atomic Access  - 00 No atomic access
 *                          - 01 Read-after-write
 *                          - 10 Write-after-read
 *                          - 11 reserved
 *     31    Valid     
 *      
 * ORx for SDRAM
 *     0-16  Address mask 
 *     17-18 Extended address mask
 *     19-21 Column address lines - 000->111 7->14
 *     23-25 Number of row address lines - 000->110 9->15
 *                                       - 111 Reserved
 *     26    Page mode select
 *     31    External address latch delay 
 *
 * ORx for GPCM Mode
 *     0-16  Address mask 
 *     17-18 Extended address mask
 *     19    Buffer Control Disable
 *     20    Chip select negation
 *     21-22 Addres to chip select setup
 *     23    Extra Address to chip select setup
 *     24-27 Cycle length in Bus clocks - 0000->1111 0->15 wait states
 *     28    External address termination
 *     29    Timing relaxed
 *     30    Extended hold time for read access
 *     31    External address latch delay  
 */

#define	M85XX_BR0(base)		(CAST(VUINT32 *)((base) + 0x5000))
#define	M85XX_OR0(base)		(CAST(VUINT32 *)((base) + 0x5004))
#define	M85XX_BR1(base)		(CAST(VUINT32 *)((base) + 0x5008))
#define	M85XX_OR1(base)		(CAST(VUINT32 *)((base) + 0x500c))
#define	M85XX_BR2(base)		(CAST(VUINT32 *)((base) + 0x5010))
#define	M85XX_OR2(base)		(CAST(VUINT32 *)((base) + 0x5014))
#define	M85XX_BR3(base)		(CAST(VUINT32 *)((base) + 0x5018))
#define	M85XX_OR3(base)		(CAST(VUINT32 *)((base) + 0x501c))
#define	M85XX_BR4(base)		(CAST(VUINT32 *)((base) + 0x5020))
#define	M85XX_OR4(base)		(CAST(VUINT32 *)((base) + 0x5024))
#define	M85XX_BR5(base)		(CAST(VUINT32 *)((base) + 0x5028))
#define	M85XX_OR5(base)		(CAST(VUINT32 *)((base) + 0x502C))
#define	M85XX_BR6(base)		(CAST(VUINT32 *)((base) + 0x5030))
#define	M85XX_OR6(base)		(CAST(VUINT32 *)((base) + 0x5034))
#define	M85XX_BR7(base)		(CAST(VUINT32 *)((base) + 0x5038))
#define	M85XX_OR7(base)		(CAST(VUINT32 *)((base) + 0x503C))

#define	M85XX_OR_PS_32          
#define	M85XX_MAR(base)		(CAST(VUINT32 *)((base) + 0x5068))
#define	M85XX_MAMR(base)	(CAST(VUINT32 *)((base) + 0x5070))
#define	M85XX_MBMR(base)	(CAST(VUINT32 *)((base) + 0x5074))
#define	M85XX_MCMR(base)	(CAST(VUINT32 *)((base) + 0x5078))
#define	M85XX_MRTPR(base)	(CAST(VUINT32 *)((base) + 0x5084))
#define	MRTPR_PTP_MASK		0xff000000
#define	MRTPR_PTP_WRITE(x)	((x << 24) & MRTPR_PTP_MASK)
#define	M85XX_MDR(base)		(CAST(VUINT32 *)((base) + 0x5088))

#define	M85XX_LSDMR(base)	(CAST(VUINT32 *)((base) + 0x5094))
#define	LSDMR_RFEN		0x40000000	/* Refresh Enable */

/* LSDMR OP - 000 Normal operation
 *          - 001 Auto Refresh  (Initialization)
 *          - 010 Self Refresh
 *          - 011 Mode Register Write (Initialization)
 *          - 100 Precharge Bank
 *          - 101 Precharge all banks (Initialization)
 *          - 110 Activate Bank
 *          - 111 Read/Write without valid transfer
 */      

#define  LSDMR_OP_MASK  0x38000000
#define  LSDMR_OP_SHIFT(x) ((x << 27) & LSDMR_OP_MASK)

/* Bank Select Multiplexed address line - 000 lines 12:13
 *                                      - 001       13:14
 *                                      - 010       14:15
 *                                      - 011       15:16
 *                                      - 100       16:17
 *                                      - 101       17:18
 *                                      - 110       18:19
 *                                      - 111       19:20
 */

#define  LSDMR_BSMA_MASK 0x00E00000
#define  LSDMR_BSMA_SHIFT(x) ((x << 23) & LSDMR_BSMA_MASK)

/* RFCR Refresh recovery 000 - reserved
 *                       001->110 - 3->8 clocks
 *                       111 - 16 clocks
 */

#define  LSDMR_RFCR_MASK 0x00038000
#define  LSDMR_RFCR_SHIFT(x) ((x << 15) & LSDMR_RFCR_MASK)
/* other LSDMR definitions not used */

#define	M85XX_LURT(base)	(CAST(VUINT32 *)((base) + 0x50A0))
#define	M85XX_LSRT(base)	(CAST(VUINT32 *)((base) + 0x50A4))
#define	M85XX_LTESR(base)	(CAST(VUINT32 *)((base) + 0x50B0))
#define	M85XX_LTEDR(base)	(CAST(VUINT32 *)((base) + 0x50B4))
#define	M85XX_LTEIR(base)	(CAST(VUINT32 *)((base) + 0x50B8))
#define	M85XX_LTEATR(base)	(CAST(VUINT32 *)((base) + 0x50BC))
#define	M85XX_LTEAR(base)	(CAST(VUINT32 *)((base) + 0x50C0))

/* LBC clock configuration */

#define	M85XX_LBCR(base)	(CAST(VUINT32 *)((base) + 0x50D0))
#define	M85XX_LCRR(base)	(CAST(VUINT32 *)((base) + 0x50D4))

/* ECM registers */

#define	ECM_OFFSET		0x1000
#define	ECMBA			(CCSBAR | ECM_OFFSET)

/* Offsets for global utils registers */
#define M85XX_DDRDLLCR(base)	(CAST(VUINT32 *)((base) + 0xE0E10))
#define M85XX_LBCDLLCR(base)    (CAST(VUINT32 *)((base) + 0xE0E20))
#define M85XX_DEVDISR(base)     (CAST(VUINT32 *)((base) + 0xE0070))

#define	DDR_OFFSET		0x2000
#define	DDRBA			(CCSBAR | DDR_OFFSET)

#define	CS0_BNDS		0x000
#define	CS1_BNDS		0x008
#define	CS2_BNDS		0x010
#define	CS3_BNDS		0x018
#define	CS0_CONFIG		0x080
#define	CS1_CONFIG		0x084
#define	CS2_CONFIG		0x088
#define	CS3_CONFIG		0x08C
#define	TIMING_CFG_1		0x108
#define	TIMING_CFG_2		0x10C
#define	DDR_SDRAM_CFG		0x110
#define	DDR_SDRAM_MODE_CFG	0x118
#define	DDR_SDRAM_INTERVAL	0x124
#define DDR_DATA_ERR_INJECT_HI  0xe00
#define DDR_DATA_ERR_INJECT_LO  0xe04
#define DDR_ECC_ERR_INJECT      0xe08
#define DDR_CAPTURE_DATA_HI     0xe20
#define DDR_CAPTURE_DATA_LO     0xe24
#define DDR_CAPTURE_ECC         0xe28
#define DDR_ERR_DETECT          0xe40
#define DDR_ERR_DISABLE         0xe44
#define DDR_ERR_INT_EN          0xe48
#define DDR_CAPTURE_ATTRIBUTES  0xe4c
#define DDR_CAPTURE_ADDRESS     0xe50
#define	DDR_ERR_SBE		0xe58


/* Offsets for PIC registers */

#define	PIC_OFFSET		0x40000
#define	PCIBA			(CCSBAR | PIC_OFFSET)


/* Memory map for the WR SBC 85xx */

/* General */

#define DDR_SDRAM_ADRS1		0x00000000	/* 256 MB DDR RAM */
#define DDR_SDRAM_ADRS2		0x10000000	/* 256 MB DDR RAM */

/* Local bus addresses */

#define BOOT_FLASH_MAP_ADRS	0xff000000	/* tlb mapped to 4GB - 16MB */
#define BOOT_FLASH_ADRS		0xff800000	/* 8 MB in 8-bit mode CS0 */
#define USR_FLASH1_ADRS		0xe0000000	/* 64 MB in 32-bit mode CS1 */
#define USR_FLASH2_ADRS		0xe4000000	/* 64 MB in 32-bit mode CS6 */
#define LOCAL_SDRAM1_ADRS	0x20000000	/* 64 MB CS3 */
#define LOCAL_SDRAM2_ADRS	0x24000000	/* 64 MB CS4 */
#define ATM_ADRS		0x80000000	/* 8 KB in 8-bit mode CS7 */
#define UTIL_ADRS		0x28000000	/* 12 MB in 8-bit mode CS5 */

#define BOOT_FLASH_WINDOW_SIZE	0x800000	/* up to 8MB of Flash */
#define BOOT_FLASH_MAP_SIZE	0x01000000	/* 16 MB for mapping */
#define USR_FLASH_WINDOW_SIZE	0x04000000	/* up to 64MB of Flash */

#define UTIL_LED7SEG		(UTIL_ADRS + 0x0)
#define UTIL_USRSW		(UTIL_ADRS + 0x100000)
#define UTIL_SR1		(UTIL_ADRS + 0x200000)
#define UTIL_SR2		(UTIL_ADRS + 0x300000)
#define UTIL_RSTCTRL		(UTIL_ADRS + 0x400000)
#define UTIL_WPPORT		(UTIL_ADRS + 0x500000)
#define UTIL_DUART1		(UTIL_ADRS + 0x700000)
#define UTIL_DUART2		(UTIL_ADRS + 0x800000)
#define UTIL_RTC		(UTIL_ADRS + 0x900000)
#define UTIL_EEPROM		(UTIL_ADRS + 0xb00000)


/* CPU type in the PVR */

#define CPU_TYPE_8540		0x80200010
#define CPU_TYPE_8560		0x80200010	/* PVRs same */
#define BRD_SR2_8540SEL_MSK	0x10
#define BRD_SR2_MODEL_8540	0x10
#define BRD_SR2_MODEL_8560	0x00
#define SYS_MODEL_8540		"MPC8540 - Wind River SBC"
#define SYS_MODEL_8560		"MPC8560 - Wind River SBC"


/* Global function registers
 *
 * PORPLL used to detect clocking ratio for CCB/CPM, including serial.
 */

#define	M85XX_PORPLLSR(base)	(CAST(VUINT32 *)((base) + 0xE0000))
#define	M85XX_PORPLLSR_E500_RATIO_MASK	0x003f0000
#define	M85XX_PORPLLSR_PLAT_RATIO_MASK	0x0000003e
#define	M85XX_PORPLLSR_E500_RATIO(base) \
        ((*M85XX_PORPLLSR(base) & M85XX_PORPLLSR_E500_RATIO_MASK) >> 16)
#define	M85XX_PORPLLSR_PLAT_RATIO(base) \
        ((*M85XX_PORPLLSR(base) & M85XX_PORPLLSR_PLAT_RATIO_MASK) >> 1)

#define M85XX_PVR(base)		(CAST(VUINT32 *)((base) + 0xE00A0))