hwconf.c

MPC8560 for vxwork BSP

/* hwconf.c - Hardware configuration support module */

/* Copyright (c) 2005-2006 Wind River Systems, Inc. */

/*
modification history
--------------------
01j,22sep06,pmr  fix WIND00065418: incorrect parameters for 8540 serial
01i,08sep06,pmr  fix brace usage.
01h,30jul06,tor  Add PCI support
01g,07feb06,wap  Add VxBus parameter table
01f,04jan06,wap  Correct TSEC setup so interrupts work
01e,26oct05,mdo  renaming header files
01d,15sep05,to   
01c,14sep05,mdo  Add vxb prefix
01b,08aug05,mdo  Change WINDBUS to VXBUS
01a,28jul05,rls  Created.
*/

#include <vxWorks.h>
#include <vxBusLib.h>
#include <hwif/vxbus/vxBus.h>
#include <hwif/vxbus/hwConf.h>
#include <hwif/util/vxbParamSys.h>
#include <drv/pci/pciAutoConfigLib.h>
#include "sysEpic.h"
#include "config.h"

const struct hcfResource motTsecHEnd0Resources[] = {
    { "regBase", HCF_RES_INT, { (void *)(CCSBAR + 0x24000) } },
    { "regBase1", HCF_RES_INT, { (void *)(CCSBAR + 0x24001) } },
    { "regBase9", HCF_RES_INT, { (void *)(CCSBAR + 0x24009) } },
    { "txInt", HCF_RES_INT, { (void *)EPIC_TSEC1TX_INT_VEC } },
    { "txIntLevel", HCF_RES_INT, { (void *)EPIC_TSEC1TX_INT_VEC } },
    { "rxInt", HCF_RES_INT, { (void *)EPIC_TSEC1RX_INT_VEC } },
    { "rxIntLevel", HCF_RES_INT, { (void *)EPIC_TSEC1RX_INT_VEC } },
    { "errInt", HCF_RES_INT, { (void *)EPIC_TSEC1ERR_INT_VEC } },
    { "errIntLevel", HCF_RES_INT, { (void *)EPIC_TSEC1ERR_INT_VEC } },
};
#define tsecHEnd0Num NELEMENTS(motTsecHEnd0Resources)

const struct hcfResource motTsecHEnd1Resources[] = {
    { "regBase", HCF_RES_INT, { (void *)(CCSBAR + 0x25000) } },
    { "txInt", HCF_RES_INT, { (void *)EPIC_TSEC2TX_INT_VEC } },
    { "txIntLevel", HCF_RES_INT, { (void *)EPIC_TSEC2TX_INT_VEC } },
    { "rxInt", HCF_RES_INT, { (void *)EPIC_TSEC2RX_INT_VEC } },
    { "rxIntLevel", HCF_RES_INT, { (void *)EPIC_TSEC2RX_INT_VEC } },
    { "errInt", HCF_RES_INT, { (void *)EPIC_TSEC2ERR_INT_VEC } },
    { "errIntLevel", HCF_RES_INT, { (void *)EPIC_TSEC2ERR_INT_VEC } },
};
#define tsecHEnd1Num NELEMENTS(motTsecHEnd1Resources)

/*
 * On the wrSbc8560 board, PHYs are physically wired according
 * to the following table:
 *
 * 		Data port pins	Management port pins	MII address
 *		--------------	--------------------	-----------
 * PHY0:	TSEC0		TSEC0			25
 * PHY1:	TSEC1		TSEC0			26
 *
 * The tricky part is that both PHYs have their management pins
 * connected to TSEC0. We have to make it look like PHY1 is connected
 * to TSEC1, so we provide a remapping resource that will cause
 * PHY1 to be attached to miibus1 instead of miibus0.
 */

const struct hcfResource phy0Resources[] = {
    { "realBus", HCF_RES_INT, { (void *)0 } },
    { "phyAddr", HCF_RES_INT, { (void *)26 } },
    { "virtBus", HCF_RES_INT, { (void *)1 } },
};
#define phy0Num NELEMENTS(phy0Resources)

IMPORT STATUS sysPciAutoconfigInclude();
IMPORT UCHAR sysPciAutoconfigIntrAssign(PCI_SYSTEM *, PCI_LOC *, UCHAR);

const struct hcfResource m85x0Pci0Resources[] = {
    { "regBase", HCF_RES_INT, { (void *)PCI_REGBASE } },
    { "mem32Addr", HCF_RES_ADDR, { (void *)PCI_MEM_ADRS } },
    { "mem32Size", HCF_RES_INT, { (void *)PCI_MEM_SIZE } },
    { "memIo32Addr", HCF_RES_ADDR, { (void *)PCI_MEMIO_ADRS } },
    { "memIo32Size", HCF_RES_INT, { (void *)PCI_MEMIO_SIZE } },
    { "io32Addr", HCF_RES_ADDR, { (void *)PCI_IO_ADRS } },
    { "io32Size", HCF_RES_INT, { (void *)PCI_IO_SIZE } }, 
    { "fbbEnable", HCF_RES_INT, { (void *)TRUE } },
    { "cacheSize", HCF_RES_INT, { (void *)(_CACHE_ALIGN_SIZE / 4) } }, 
    { "maxLatAllSet", HCF_RES_INT, { (void *)PCI_LAT_TIMER } },
    { "autoIntRouteSet", HCF_RES_INT, { (void *)TRUE } }, 
    { "includeFuncSet", HCF_RES_ADDR, { (void *)sysPciAutoconfigInclude } },
    { "intAssignFuncSet", HCF_RES_ADDR, {(void *)sysPciAutoconfigIntrAssign }},
    /* non vxbPciAutoConfig() values */
    { "pimmrBase", HCF_RES_ADDR, { (void *)PCI_BRIDGE_PIMMR_BASE_ADRS } },
    { "lclMemAddr", HCF_RES_ADDR, { (void *)LOCAL_MEM_LOCAL_ADRS } },
    { "lclMemMapSize", HCF_RES_INT, { (void *)(512 * 1024 * 1024) } },
    { "mstrMemBus", HCF_RES_ADDR, { (void *)PCI_MSTR_MEM_BUS } },
};
#define m85x0Pci0Num NELEMENTS(m85x0Pci0Resources)

#ifdef INCLUDE_CPM
const struct hcfResource ns165500Resources[] = { 
    { "regBase",     HCF_RES_INT, {(void *)COM1_BRD_ADRS} },
    { "irq",         HCF_RES_INT, {(void *)COM1_INT_VEC} },
    { "irqLevel",    HCF_RES_INT, {(void *)COM1_INT_LVL} },
    { "clkFreq",     HCF_RES_INT, {(void *)XTAL_BRD} },
    { "regInterval", HCF_RES_INT, {(void *)UART_REG_INTVL} }
};
#define ns165500Num NELEMENTS(ns165500Resources)

const struct hcfResource ns165501Resources[] = { 
    { "regBase",     HCF_RES_INT, {(void *)COM2_BRD_ADRS} },
    { "irq",         HCF_RES_INT, {(void *)COM2_INT_VEC} },
    { "irqLevel",    HCF_RES_INT, {(void *)COM2_INT_LVL} },
    { "clkFreq",     HCF_RES_INT, {(void *)XTAL_BRD} },
    { "regInterval", HCF_RES_INT, {(void *)UART_REG_INTVL} }
};
#define ns165501Num NELEMENTS(ns165501Resources)

#else /* ! defined INCLUDE_CPM */
const struct hcfResource ns165500Resources[] = { 
    { "regBase",     HCF_RES_INT, {(void *)COM1_CHIP_ADRS} },
    { "irq",         HCF_RES_INT, {(void *)EPIC_DUART_INT_VEC} },
    { "irqLevel",    HCF_RES_INT, {(void *)EPIC_DUART_INT_VEC} },
    { "clkFreq",     HCF_RES_INT, {(void *)PLAT_FREQ_DEFAULT} },
    { "regInterval", HCF_RES_INT, {(void *)UART_REG_INTVL} }
};
#define ns165500Num NELEMENTS(ns165500Resources)

const struct hcfResource ns165501Resources[] = { 
    { "regBase",     HCF_RES_INT, {(void *)COM2_CHIP_ADRS} },
    { "irq",         HCF_RES_INT, {(void *)EPIC_DUART_INT_VEC} },
    { "irqLevel",    HCF_RES_INT, {(void *)EPIC_DUART_INT_VEC} },
    { "clkFreq",     HCF_RES_INT, {(void *)PLAT_FREQ_DEFAULT} },
    { "regInterval", HCF_RES_INT, {(void *)UART_REG_INTVL} }
};
#define ns165501Num NELEMENTS(ns165501Resources)

#endif /* INCLUDE_CPM */

const struct hcfResource m85xxCCSR0Resources[] = {
    { "regBase", HCF_RES_INT, { (void *)CCSBAR  } },
    { "LAWBAR0",    HCF_RES_STRING,     { (void *)"reserved" } },
    { "LAWBAR1",    HCF_RES_STRING,     { (void *)"reserved" } },
    { "LAWBAR2",    HCF_RES_STRING,     { (void *)NULL } },
    { "LAWBAR3",    HCF_RES_STRING,     { (void *)"reserved" } },
    { "LAWBAR4",    HCF_RES_STRING,     { (void *)"m8560Rio" } },
    { "LAWBAR5",    HCF_RES_STRING,     { (void *)"m85x0Pci" } },
    { "LAWBAR6",    HCF_RES_STRING,     { (void *)"m85x0Pci" } },
    { "LAWBAR7",    HCF_RES_STRING,     { (void *)"m85x0Pci" } }
};
#define m85xxCCSR0Num NELEMENTS(m85xxCCSR0Resources)

const struct hcfDevice hcfDeviceList[] = {
    { "mottsecHEnd", 0, VXB_BUSID_PLB, 0, tsecHEnd0Num, motTsecHEnd0Resources },
    { "mottsecHEnd", 1, VXB_BUSID_PLB, 0, tsecHEnd1Num, motTsecHEnd1Resources },
    { "m85x0Pci", 0, VXB_BUSID_PLB,0, m85x0Pci0Num, m85x0Pci0Resources },
    { "m85xxCCSR", 0, VXB_BUSID_PLB,0, m85xxCCSR0Num, m85xxCCSR0Resources },
    { "phy", 0, VXB_BUSID_MII, 0, phy0Num, phy0Resources },
    { "ns16550", 0, VXB_BUSID_PLB, 0, ns165500Num, ns165500Resources },
#ifdef INCLUDE_MEZZ_COM2
    { "ns16550", 1, VXB_BUSID_PLB, 0, ns165501Num, ns165501Resources },
#endif /* INCLUDE_MEZZ_COM2 */
};

const int hcfDeviceNum = NELEMENTS(hcfDeviceList);

VXB_INST_PARAM_OVERRIDE sysInstParamTable[] =
    {
    { NULL, 0, NULL, VXB_PARAM_END_OF_LIST, {(void *)0} }
    };