target.ref

MPC8560 for vxwork BSP

             3.2.5.2 In the "Programming Algorithm" group in, the edit box
                     press on the "Select" button, and select the 
                     following Flash device:

                     For the 8MB Flash: "INTEL V28F640Jx (8192 x 8) 1 Device"

             3.2.5.3 Set the proper address of the Flash to "FF800000", check
                     the "Erase All" radio button,and set the
                     "Available RAM Workspace" setting to "00002000", set the
                     "Bytes Of Target RAM Required" to "60000".

             3.2.5.4 Press the "Erase and Program" button.

             3.2.5.5 Now the Flash memory is programmed with the new boot
                     program.

4. Running the VxWorks Boot ROM program:

   4.1 Disconect the WindPowerICE if it is still connected to the
       board, because if connected, it can stop the processor at 
       the first instruction in some cases.

   4.2 Connecting the Ethernet channel and the serial channel:

       4.2.1 First, connect the supplied serial cable with the board. The 
             cable should be connected to the mini-DB9 connector on the 
             edge of the card.  Connect the other end of the cable with 
             a standard DB9 connector directly to the host RS232 port.  
             An optional DB25 adaptor may be needed.  The COM port should
             be set to  data bits, 1 stop bit, hardware handshaking, and 
             parity disabled.  The baud rate is 9600 bps.  

       4.2.2 Second, connect an RJ45 ethernet cable to the first TSEC port
             adjacent to the mini-DB9 serial port.
             
   4.3 Launch a terminal program on the host, and configures it according 
       to 8 data bits, 1 stop bit, hardware handshaking, and parity 
       disabled.  Again, the baud rate is 9600 bps.

   4.4 If the board is not already powered off, turn it off momentarily.
       Power on the board and in about 15 seconds,  you should see 
       characters printed to the terminal window, counting down to boot.
       Press any key to stop the count down. Now follow the instructions
       in the "Getting Started" chapter of the "VxWorks Programmer's
       Guide" for more detail on how to configure vxWorks.

5. Running the VxWorks without a VxWorks Boot ROM:

   VisionCLICK or WindPowerIDE can download a vxWorks image to the WR
   SBC 8540 or SBC 8560 through the JTAG interface without using the
   VxWorks bootrom.

   The requirement to define NO_VX_BOOTROM (in earlier version of the
   BSP) to run VxWorks without the VxWorks bootrom is no longer needed.
   VisionCLICK or WindPowerIDE should now be able to download and boot
   a standard vxWorks image.  For network to use the bootline correctly,
   USE_ALT_BOOTLINE should be defined in config.h and have ALT_BOOT_LINE
   set to the correct network parameters.

\sh BOOT DEVICES
The supported boot devices are:
\cs
	mottsec - 10/100/1000 Triple Speed Ethernet Controller
	motfcc - 10/100 ethernet (on MPC8560 only, requires mezz card)
\ce

FEATURES
This section describes the support and unsupported features of the wrSbc85xx

\sh Supported Features

The supported features of the SBC85xx board are:
        MPC 8540/8560 processors
	Board Initialization.
	MMU support.
	Cache support.
	L2 Cache support.
	L2 SRAM support.
	Decrementer timer is used to implement a System Clock.
	Timestamp clock.
	MPC8560 10/100 FCC Ethernet Controller.
	On-chip Programmable Interrupt Controller.
	DDR SDRAM (up to 512 MB Memory SODIMM).
	Local bus SDRAM (up to 128 MB Memory SODIMM).
	FLASH (up to 64 MB SODIMM).
	FLASH 8MB on board, also used by bootrom.
	Saving boot parameters on the EEPROM when using vxWorks bootrom.

The VxBus device drivers used for on-board devices include:
	m85x0Pci: PCI/PCI-X
	motTsecHEnd: On-chip 10/100/1000 Triple Speed Ethernet Controller.
	ns16550sio: MPC8540 DUART
	ns16550sio: SC16C2550 DUART

\sh Unsupported Features

The items not supported by the BSP of the wrSbc85xx are:
	RapidIO
	ATM channels
	10/100 maintenance port (MPC8540 only)

HARDWARE DETAILS
This section documents the details of the device drivers and board
hardware elements for the wrSbc85xx.

\sh Devices
The chip drivers included are:

\ts
sysNvRam.c|Generic non-volatile RAM library
m85xxTimer.c|system clock,aux clock, and timestamp driver using PPC decrementer
cfiscs.c|Flash access routines
sysEpic.c|Motorola MPC107 PIC interrupt controller driver
sysDuart.c|prepares serial driver
sysL2Cache.c|L2 cache library
motFcc2End.c|FCC END driver
m85xxCpmIntrCtl.c|CPM interrupt controller driver
\te

The BSP configures the on-chip or on-board DUART to implement a console
device and the TSEC as an Ethernet.  The SCC device in the CPM on the MPC8560
is not actually used by this BSP, although a sample file sysScc.c is included.

VxBus support is standard in this BSP, therefore additional
VxBus drivers can be used with this BSP.  This may be useful,
for example, for PCI devices.

\sh Support for L2 Cache
L2 Cache is configured with callback function
pointers for L2 cache Global Invalidation, L2 Cache Enable, L2 Cache
Flush and L2 Cache Disable are intialized in sysHwInit().  By default, the
256 KB L2 is configured to 128 KB of cache and 128 KB of SRAM.  If a
different configuration is desired, a new bootrom image should be used
to match the RAM image configuration of L2.

\sh Support for Signal Processing Engine (SPE)
MPC8540 and MPC8560 support an SPE APU that implements scalar and
vector processing. Support for SPE is now available, but an
SPE aware compiler must be used to create applications that
use SPE instructions. The SPE support can be enabled by
defining INCLUDE_SPE in config.h, set by default.

\sh Operating Speed
The processor has built-in PLL circuits to control the operating speed of 
the Core Complex Bus (CCB) as well as the E500 core.  The board uses a 
33.33 MHz crystal and doubles it to 66.66 MHz before feeding into the 
processor.  This processor clock input is referred to as the system clock
(SYSCLK).  SW7 or SW9 (depending on board revision) controls the PLL to
provide different operating speed combinations.  This BSP supports a CCB
speed of 200 MHz or 266 MHz.  At time of testing, a core speed of up to 
666 MHz is officially supported by the hardware.  An earlier revision of 
this file erroneously indicated DIP switch setting of speed of up to 
933MHz.  Although overclocking may work in some cases, they are not 
supported by the BSP and/or the hardware.  Please verify the processor 
markings with its corresponding electrical specification.

The serial console of the wrSbc8540 uses the DUART device of the MPC8540,
whose clock is dependent on the CCB frequency.  This BSP can auto-sense 
the CCB:SYSCLK ratio to configure for a baud rate of 9600 bps.  The wrSbc8560
uses a dedicate clock on board and will also default to 9600 bps.

All time base facilities of the MPC85xx, including the decrementer timer
used by VxWorks, is also based on the CCB frequency.  If the auto-sense 
fail to report a proper ratio, it will default to a preset value defined
by PLAT_FREQ_DEFAULT in config.h.  To override the auto-sense feature,
PLAT_FREQ_OVERRIDE should be defined.

\sh Default Memory Map
\cs
Memory Map from CPU point of view

Chip Select	Start               Size         Access to
---------------------------------------------------------------------
n/a             0xFE000000           1MB         CCSR (Ctrl/Config/Status)
n/a             0x7FFC0000         256KB         L2SRAM
MCS0            0x00000000         256MB         DDR SDRAM SODIMM
MCS1            0x10000000         256MB         DDR SDRAM SODIMM
CS0             0xFF800000           8MB         On Board FLASH
CS1             0xE4000000          64MB         User FLASH SODIMM
CS2             n/a                  n/a         Not used
CS3             0x20000000          64MB         Local SDRAM SODIMM
CS4             0x24000000          64MB         Local SDRAM SODIMM
CS5             0x28000000           8KB         7-Segment Display
                0x28100000           8KB         User Switches
                0x28200000           8KB         Status Register 1
                0x28300000           8KB         Status Register 2
                0x28400000           8KB         Reset Control Register
                0x28500000           8KB         Wind Power Port
                0x28700000           8KB         DUART A COM1 (wrSbc8560)
                0x28800000           8KB         DUART B COM2 (wrSbc8560)
                0x28900000           8KB         Real Time Clock
                0x28B00000           8KB         8KB EEPROM
CS6             0xE0000000          64MB         User FLASH SODIMM
CS7             0x80000000           8KB         ATM
\ce

\sh Booting
Upon reset, the MPC85xx begins executing from 0xffff_fffc.  Only the last
4KB of memory is mapped by the TLB.  The instruction at 0xffff_fffc branches
to resetEntry() located at the last 2KB of memory to begin initialization
and mapping of memory static TLB entries.  The DDR SDRAM is then mapped to
0x0 where the vectors are setup to use and execution is then transfered
to the RAM after copying and uncompressing if necessary.

The bootrom for the wrSbc8560 allows loading with either the TSEC or the FCC
ethernet channel.  In the boot dialog, they correspond to the "mottsec0" and
the "motfcc0" devices.  To switch between the two boot devices after a load
is attempted, a hard reset or power cycle is necessary in order for the 
device to function properly.  After the reset, press a key to stop the 
countdown, then use the "c" command to change the boot device to the desired 
network device.

The wrSbc8560 also allows the use of a mezzanine card that has the FCC 
ethernet ports, and the second serial RS-232 port.  If a mezzanine card
with a second serial RS-232 port is plugged in, INCLUDE_MEZZ_COM2 should
be defined in config.h.

If a different network setting (the bootline) is to be used after the
vxWorks image gets loaded, the macro USE_ALT_BOOTLINE can be defined in 
config.h.  The configuration defined by ALT_BOOT_LINE will be used in
place of the value stored in the NVRAM.

\sh DDR SDRAM Size
Initial boards and bsp are supplied with a 512MB DDR SDRAM SODIMM.

\sh Local Bus SDRAM Size
Initial boards and bsp are supplied with a 64MB or 128MB SDRAM SODIMM.

\sh Network Configuration
The Ethernet uses an RJ45 (twisted pair) jack and can be used with either
10baseT or 100baseTX. The TSEC port also allows 1000baseT.  The hardware
will auto-negotiate and configures the port accordingly.

\sh  NVRAM Support 
This BSP uses NvRam on the 8KB EEPROM device.  The bootline is stored
at the beginning of the NvRam, and boot device MAC address is stored
at offset 0x200.

\sh ROM Considerations
bootrom_uncmp.bin is provided with this BSP. The bootrom is configured to 
a ROM base address of 0x0. When programing the bootrom to the FLASH an offset
of 0xFFF00000 need to be given.

\sh BOOT FLASH
The BSP configures to use the 8MByte On Board Flash. There is also a 64/128MB
SODIMM flash device supported on the board, but only the 8MB flash is supported
for booting.

\sh Serial Configuration
The UART devices are configured with 8 data bits, 1 stop bit, hardware
handshaking, and parity disabled.  They operate at 9600 bps.  Both the
on-chip DUART on the MPC8540 or the on-board DUART with the MPC8560 are
routed to the same ports.

As described in the Operating Speed section, the serial console of the
wrSbc8540 uses the DUART device of the MPC8540, whose clock is dependent 
on the CCB frequency.  This BSP can auto-sense the CCB:SYSCLK ratio to 
configure for a baud rate of 9600 bps.  The wrSbc8560 uses a dedicate clock 
on board and will also default to 9600 bps.

Also, be reminded that the wrSbc8560 also allows the use of a mezzanine 
card that has a second serial RS-232 port.  If a mezzanine card with
a second serial RS-232 port is plugged in, INCLUDE_MEZZ_COM2 should
be defined in config.h.

\sh Programable Interrupt Controller
The PIC driver provided by this BSP supports all internal and external
interrupt sources.  It can also be configured to route such sources to
the critical interrupt pin, as well as acting as handling the critical
interrupts.  However, since critical interrupts are routed directly to