📄 s12_crg.c
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//=============================================================================
// File: S12_CRG.C - V1.00
// Rem.: The ACPRD Project Page on the Web -> http://hc12web.de/acprd
//=============================================================================
//-- Includes -----------------------------------------------------------------
#include "hcs12dp256.h"
#include "s12_crg.h"
//-- Code ---------------------------------------------------------------------
void initPLL(void) {
CLKSEL &= ~BM_PLLSEL; // make sure PLL is *not* in use
PLLCTL |= BM_PLLON+BM_AUTO; // enable PLL module, Auto Mode
REFDV = S12_REFDV; // set up Reference Divider
SYNR = S12_SYNR; // set up Synthesizer Multiplier
// the following dummy write has no effect except consuming some cycles,
// this is a workaround for erratum MUCTS00174 (mask set 0K36N only)
// CRGFLG = 0;
while((CRGFLG & BM_LOCK) == 0) ; // wait until PLL is locked
CLKSEL |= BM_PLLSEL; // switch over to PLL clock
}
//=============================================================================
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