📄 s12_crg.h
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//=============================================================================
// File: S12_CRG.H - V1.00
// Rem.: The ACPRD Project Page on the Web -> http://hc12web.de/acprd
//=============================================================================
#ifndef __S12_CRG_H
#define __S12_CRG_H
//-- CRG Bit Mask Definitions -------------------------------------------------
// Bits in CRGFLG:
#define BM_RTIF 0x80
#define BM_PORF 0x40
//#define reserved 0x20
#define BM_LOCKIF 0x10
#define BM_LOCK 0x08
#define BM_TRACK 0x04
#define BM_SCMIF 0x02
#define BM_SCM 0x01
// Bits in CRGINT:
#define BM_RTIE 0x80
//#define reserved 0x40
//#define reserved 0x20
#define BM_LOCKIE 0x10
//#define reserved 0x08
//#define reserved 0x04
#define BM_SCMIE 0x02
//#define reserved 0x01
// Bits in CLKSEL:
#define BM_PLLSEL 0x80
#define BM_PSTP 0x40
#define BM_SYSWAI 0x20
#define BM_ROAWAI 0x10
#define BM_PLLWAI 0x08
#define BM_CWAI 0x04
#define BM_RTIWAI 0x02
#define BM_COPWAI 0x01
// Bits in PLLCTL:
#define BM_CME 0x80
#define BM_PLLON 0x40
#define BM_AUTO 0x20
#define BM_ACQ 0x10
//#define reserved 0x08
#define BM_PRE 0x04
#define BM_PCE 0x02
#define BM_SCME 0x01
//-- Defines ------------------------------------------------------------------
// set the following values according to system requirements:
//
#define S12_OSCCLK 16000000 // input frequency from Xtal/Osc
#define S12_REFCLK 8000000 // PLL internal reference clock
#define S12_PLLCLK 48000000 // desired output frequency of PLL
// PLL clock generation formula, according to CRG Block User Guide:
// PLLCLK = OSCCLK * 2(SYNR+1) / (REFDV+1)
//
#define S12_REFDV ((S12_OSCCLK/S12_REFCLK)-1)
#define S12_SYNR ((S12_PLLCLK/(2*S12_REFCLK))-1)
#define S12_ECLK (S12_PLLCLK/2) // final bus clock frequency (ECLK)
//#define S12_ECLK (S12_OSCCLK/2) // bus clock if PLL not in use / off
//-- Function Prototypes ------------------------------------------------------
void initPLL(void);
#endif //__S12_CRG_H ==========================================================
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