📄 hardware.lst
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/////////////////////////////////////////////////////////////////
// Note: This register map to the P_INT_Ctrl(0x7010)
// User's interrupt setting have to combine with this register
// while co-work with SACM library.
//
// See. following function for example:
// F_SP_SACM_A2000_Init_:
// F_SP_SACM_S480_Init_:
// F_SP_SACM_S240_Init_:
// F_SP_SACM_MS01_Init_:
// F_SP_SACM_DVR_Init_:
//////////////////////////////////////////////////
0000044F .IRAM
.PUBLIC R_InterruptStatus
0000044F 00 00 .VAR R_InterruptStatus = 0 //
//////////////////////////////////////////////////
.DEFINE C_RampDelayTime 32
.DEFINE C_QueueSize 144
00000450 00 00 .VAR R_Queue
00000451 00 00 00 00 .DW C_QueueSize-1 DUP(0)
00 00 00 00
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00 00
000004E0 00 00 .VAR R_ReadIndex
000004E1 00 00 .VAR R_WriteIndex
0000AB7B .CODE
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,r2
///////////////////////////////////////////
_SP_InitQueue: .PROC
_SP_InitQueue_A2000:
_SP_InitQueue_S480:
_SP_InitQueue_S240:
_SP_InitQueue_MS01:
_SP_InitQueue_DVR:
F_SP_InitQueue_A2000:
F_SP_InitQueue_S480:
F_SP_InitQueue_S240:
F_SP_InitQueue_MS01:
F_SP_InitQueue_DVR:
F_SP_InitQueue:
0000AB7B 09 93 50 04 r1 = R_Queue
0000AB7D 40 94 r2 = 0
L_ClearQueueLoop?:
0000AB7E D1 D4 [r1++] = r2
0000AB7F 09 43 E0 04 cmp r1, R_Queue+C_QueueSize
0000AB81 44 4E jne L_ClearQueueLoop?
0000AB82 40 92 r1 = 0
0000AB83 19 D3 E0 04 [R_ReadIndex] = r1
0000AB85 19 D3 E1 04 [R_WriteIndex] = r1
0000AB87 90 9A RETF
.ENDP
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_A2000:
F_SP_ReadQueue_S480:
F_SP_ReadQueue_S240:
F_SP_ReadQueue_MS01:
F_SP_ReadQueue_DVR:
F_SP_ReadQueue:
0000AB88 12 95 E0 04 r2 = [R_ReadIndex]
0000AB8A 12 45 E1 04 cmp r2,[R_WriteIndex]
0000AB8C 0D 5E je L_RQ_QueueEmpty
0000AB8D 0A 05 50 04 r2 += R_Queue // get queue data address
0000AB8F C2 92 r1 = [r2]
0000AB90 12 95 E0 04 r2 = [R_ReadIndex]
0000AB92 41 04 r2 += 1
0000AB93 0A 45 90 00 cmp r2, C_QueueSize
0000AB95 01 4E jne L_RQ_NotQueueBottom
0000AB96 40 94 r2 = 0
L_RQ_NotQueueBottom:
0000AB97 1A D5 E0 04 [R_ReadIndex] = r2
//r2 = 0x0000 // get queue data
0000AB99 90 9A retf
L_RQ_QueueEmpty:
//r2 = 0x8000 // queue empty
0000AB9A 90 9A retf
///////////////////////////////////////////
// Function: Get a data from Queue but do
// not change queue index
// R1: output
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_NIC:
F_SP_ReadQueue_NIC_A2000:
F_SP_ReadQueue_NIC_S480:
F_SP_ReadQueue_NIC_S240:
F_SP_ReadQueue_NIC_MS01:
F_SP_ReadQueue_NIC_DVR:
0000AB9B 12 95 E0 04 r2 = [R_ReadIndex]
0000AB9D 12 45 E1 04 cmp r2,[R_WriteIndex]
0000AB9F 03 5E je L_RQ_QueueEmpty?
0000ABA0 0A 05 50 04 r2 += R_Queue // get queue data index
0000ABA2 C2 92 r1 = [r2]
L_RQ_QueueEmpty?:
0000ABA3 90 9A RETF
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2
///////////////////////////////////////////
F_SP_WriteQueue_A2000:
F_SP_WriteQueue_S480:
F_SP_WriteQueue_S240:
F_SP_WriteQueue_MS01:
F_SP_WriteQueue_DVR:
F_SP_WriteQueue:
0000ABA4 12 95 E1 04 r2 = [R_WriteIndex] // put data to queue
0000ABA6 0A 05 50 04 r2 += R_Queue
0000ABA8 C2 D2 [r2] = r1
0000ABA9 12 95 E1 04 r2 = [R_WriteIndex]
0000ABAB 41 04 r2 += 1
0000ABAC 0A 45 90 00 cmp r2, C_QueueSize
0000ABAE 01 4E jne L_WQ_NotQueueBottom
0000ABAF 40 94 r2 = 0
L_WQ_NotQueueBottom:
0000ABB0 1A D5 E1 04 [R_WriteIndex] = r2
0000ABB2 90 9A RETF
///////////////////////////////////////////
// Function: Test Queue Status
// o/p: R1
// Destory: R1
///////////////////////////////////////////
F_SP_TestQueue_A2000:
F_SP_TestQueue_S480:
F_SP_TestQueue_S240:
F_SP_TestQueue_MS01:
F_SP_TestQueue_DVR:
F_SP_TestQueue:
//... Test Queue Empty ...
0000ABB3 11 93 E0 04 r1 = [R_ReadIndex]
0000ABB5 11 43 E1 04 cmp r1,[R_WriteIndex]
0000ABB7 12 5E je L_TQ_QueueEmpty
//... Test Queue Full ...
0000ABB8 11 93 E0 04 r1 = [R_ReadIndex] // For N Queue Full: 1.R=0 and W=N-1 2. R<>0 and W=R-1
0000ABBA 05 4E jnz L_TQ_JudgeCond2
0000ABBB 11 93 E1 04 r1 = [R_WriteIndex]
0000ABBD 09 43 8F 00 cmp r1, C_QueueSize-1 // Cond1
0000ABBF 08 5E je L_TQ_QueueFull
L_TQ_JudgeCond2:
0000ABC0 11 93 E0 04 r1 = [R_ReadIndex]
0000ABC2 41 22 r1 -=1
0000ABC3 11 43 E1 04 cmp r1,[R_WriteIndex]
0000ABC5 02 5E je L_TQ_QueueFull
0000ABC6 40 92 r1 = 0 // not Full, not empty
0000ABC7 90 9A retf
L_TQ_QueueFull:
0000ABC8 41 92 r1 = 1 // full
0000ABC9 90 9A retf
L_TQ_QueueEmpty:
0000ABCA 42 92 r1 = 2 // empty
0000ABCB 90 9A retf
///////////////////////////////////////////////////////////////////////////////
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