📄 ledt18.rpt
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-- Node name is ':4819'
-- Equation name is '_LC6_D22', type is buried
_LC6_D22 = LCELL( _EQ053);
_EQ053 = !_LC1_D26 & _LC5_D22
# f11 & _LC1_D26;
-- Node name is ':4822'
-- Equation name is '_LC7_D22', type is buried
_LC7_D22 = LCELL( _EQ054);
_EQ054 = !_LC3_D26 & _LC6_D22
# f11 & _LC5_D31;
-- Node name is ':4831'
-- Equation name is '_LC2_D22', type is buried
_LC2_D22 = LCELL( _EQ055);
_EQ055 = f12 & _LC4_D26
# _LC7_D21;
-- Node name is ':4834'
-- Equation name is '_LC3_D22', type is buried
_LC3_D22 = LCELL( _EQ056);
_EQ056 = !_LC1_D26 & _LC2_D22
# f10 & _LC1_D26;
-- Node name is ':4837'
-- Equation name is '_LC4_D22', type is buried
_LC4_D22 = LCELL( _EQ057);
_EQ057 = _LC3_D22 & !_LC3_D26
# f10 & _LC5_D31;
-- Node name is ':4846'
-- Equation name is '_LC6_D35', type is buried
_LC6_D35 = LCELL( _EQ058);
_EQ058 = f11 & _LC4_D26
# _LC7_D21;
-- Node name is ':4849'
-- Equation name is '_LC7_D35', type is buried
_LC7_D35 = LCELL( _EQ059);
_EQ059 = !_LC1_D26 & _LC6_D35
# f9 & _LC1_D26;
-- Node name is ':4852'
-- Equation name is '_LC8_D35', type is buried
_LC8_D35 = LCELL( _EQ060);
_EQ060 = !_LC3_D26 & _LC7_D35
# f9 & _LC5_D31;
-- Node name is ':4865'
-- Equation name is '_LC7_D34', type is buried
_LC7_D34 = LCELL( _EQ061);
_EQ061 = !f17 & _LC1_D26
# !f0 & _LC1_D26;
-- Node name is ':4866'
-- Equation name is '_LC2_D35', type is buried
_LC2_D35 = LCELL( _EQ062);
_EQ062 = f10 & !_LC1_D26 & _LC4_D26
# !_LC1_D26 & _LC7_D21;
-- Node name is ':4867'
-- Equation name is '_LC3_D35', type is buried
_LC3_D35 = LCELL( _EQ063);
_EQ063 = _LC2_D35 & !_LC3_D26
# !_LC3_D26 & _LC7_D34
# _LC5_D31;
-- Node name is ':4868'
-- Equation name is '_LC5_D31', type is buried
_LC5_D31 = LCELL( _EQ064);
_EQ064 = _LC1_D31 & _LC3_D26
# _LC3_D26 & _LC6_D21
# _LC3_D26 & _LC7_D25;
-- Node name is ':4881'
-- Equation name is '_LC3_D31', type is buried
_LC3_D31 = LCELL( _EQ065);
_EQ065 = f9 & !_LC1_D26 & _LC4_D26
# !_LC1_D26 & _LC7_D21;
-- Node name is ':4882'
-- Equation name is '_LC4_D35', type is buried
_LC4_D35 = LCELL( _EQ066);
_EQ066 = !_LC3_D26 & _LC7_D34
# !_LC3_D26 & _LC3_D31
# _LC5_D31;
-- Node name is '~4900~1'
-- Equation name is '~4900~1', location is LC6_D31, type is buried.
-- synthesized logic cell
_LC6_D31 = LCELL( _EQ067);
_EQ067 = f8 & _LC4_D26
# f8 & _LC1_D26
# !_LC1_D26 & _LC7_D21;
-- Node name is '~4900~2'
-- Equation name is '~4900~2', location is LC8_D20, type is buried.
-- synthesized logic cell
_LC8_D20 = LCELL( _EQ068);
_EQ068 = !_LC3_D26 & _LC6_D31
# f8 & _LC5_D31;
-- Node name is '~4915~1'
-- Equation name is '~4915~1', location is LC6_D20, type is buried.
-- synthesized logic cell
_LC6_D20 = LCELL( _EQ069);
_EQ069 = !_LC1_D26 & _LC7_D21
# f7 & _LC4_D26
# f7 & _LC1_D26;
-- Node name is '~4915~2'
-- Equation name is '~4915~2', location is LC7_D20, type is buried.
-- synthesized logic cell
_LC7_D20 = LCELL( _EQ070);
_EQ070 = !_LC3_D26 & _LC6_D20
# f7 & _LC5_D31;
-- Node name is '~4930~1'
-- Equation name is '~4930~1', location is LC4_D20, type is buried.
-- synthesized logic cell
_LC4_D20 = LCELL( _EQ071);
_EQ071 = !_LC1_D26 & _LC7_D21
# f6 & _LC4_D26
# f6 & _LC1_D26;
-- Node name is '~4930~2'
-- Equation name is '~4930~2', location is LC5_D20, type is buried.
-- synthesized logic cell
_LC5_D20 = LCELL( _EQ072);
_EQ072 = !_LC3_D26 & _LC4_D20
# f6 & _LC5_D31;
-- Node name is '~4945~1'
-- Equation name is '~4945~1', location is LC7_D26, type is buried.
-- synthesized logic cell
_LC7_D26 = LCELL( _EQ073);
_EQ073 = !_LC1_D26 & _LC7_D21
# f5 & _LC4_D26
# f5 & _LC1_D26;
-- Node name is '~4945~2'
-- Equation name is '~4945~2', location is LC6_D26, type is buried.
-- synthesized logic cell
_LC6_D26 = LCELL( _EQ074);
_EQ074 = !_LC3_D26 & _LC7_D26
# f5 & _LC5_D31;
-- Node name is '~4960~1'
-- Equation name is '~4960~1', location is LC6_D25, type is buried.
-- synthesized logic cell
_LC6_D25 = LCELL( _EQ075);
_EQ075 = !_LC1_D26 & _LC7_D21
# f4 & _LC4_D26
# f4 & _LC1_D26;
-- Node name is '~4960~2'
-- Equation name is '~4960~2', location is LC8_D25, type is buried.
-- synthesized logic cell
_LC8_D25 = LCELL( _EQ076);
_EQ076 = !_LC3_D26 & _LC6_D25
# f4 & _LC5_D31;
-- Node name is '~4975~1'
-- Equation name is '~4975~1', location is LC6_D34, type is buried.
-- synthesized logic cell
_LC6_D34 = LCELL( _EQ077);
_EQ077 = !_LC1_D26 & _LC7_D21
# f3 & _LC4_D26
# f3 & _LC1_D26;
-- Node name is '~4975~2'
-- Equation name is '~4975~2', location is LC8_D34, type is buried.
-- synthesized logic cell
_LC8_D34 = LCELL( _EQ078);
_EQ078 = !_LC3_D26 & _LC6_D34
# f3 & _LC5_D31;
-- Node name is '~4990~1'
-- Equation name is '~4990~1', location is LC2_D26, type is buried.
-- synthesized logic cell
_LC2_D26 = LCELL( _EQ079);
_EQ079 = !_LC1_D26 & _LC7_D21
# f2 & _LC4_D26
# f2 & _LC1_D26;
-- Node name is '~4990~2'
-- Equation name is '~4990~2', location is LC8_D26, type is buried.
-- synthesized logic cell
_LC8_D26 = LCELL( _EQ080);
_EQ080 = _LC2_D26 & !_LC3_D26
# f2 & _LC5_D31;
-- Node name is '~5005~1'
-- Equation name is '~5005~1', location is LC8_D31, type is buried.
-- synthesized logic cell
_LC8_D31 = LCELL( _EQ081);
_EQ081 = !_LC1_D26 & _LC7_D21
# f1 & _LC4_D26
# f1 & _LC1_D26;
-- Node name is '~5005~2'
-- Equation name is '~5005~2', location is LC3_D34, type is buried.
-- synthesized logic cell
_LC3_D34 = LCELL( _EQ082);
_EQ082 = !_LC3_D26 & _LC8_D31
# f1 & _LC5_D31;
Project Information d:\three\horse\ledt18.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 27,901K
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