📄 ledt18.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\three\horse\ledt18.rpt
ledt18
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - D 33 DFFE + 0 1 0 18 f_scan1 (:23)
- 7 - D 36 DFFE 0 5 1 5 f17 (:24)
- 1 - D 36 DFFE 0 5 1 6 f16 (:25)
- 6 - D 27 DFFE 0 5 1 6 f15 (:26)
- 1 - D 27 DFFE 0 5 1 6 f14 (:27)
- 1 - D 21 DFFE 0 5 1 6 f13 (:28)
- 1 - D 22 DFFE 0 5 1 6 f12 (:29)
- 8 - D 22 DFFE 0 5 1 6 f11 (:30)
- 1 - D 35 DFFE 0 5 1 6 f10 (:31)
- 5 - D 35 DFFE 0 5 1 6 f9 (:32)
- 7 - D 31 DFFE 0 5 1 5 f8 (:33)
- 1 - D 20 DFFE 0 5 1 5 f7 (:34)
- 2 - D 20 DFFE 0 5 1 5 f6 (:35)
- 3 - D 20 DFFE 0 5 1 5 f5 (:36)
- 5 - D 25 DFFE 0 5 1 5 f4 (:37)
- 4 - D 25 DFFE 0 5 1 5 f3 (:38)
- 5 - D 34 DFFE 0 5 1 5 f2 (:39)
- 1 - D 34 DFFE 0 5 1 5 f1 (:40)
- 2 - D 34 DFFE 0 5 1 4 f0 (:41)
- 3 - D 33 DFFE + 0 2 0 1 d_ff2 (:43)
- 2 - D 33 DFFE + 0 1 0 1 d_ff1 (:44)
- 1 - D 33 DFFE + 0 0 0 2 d_ff0 (:45)
- 1 - D 31 OR2 s 0 4 0 2 ~580~1
- 6 - D 21 OR2 s 0 4 0 2 ~580~2
- 1 - D 25 OR2 s 0 4 0 1 ~580~3
- 3 - D 25 OR2 s 0 4 0 1 ~580~4
- 7 - D 25 OR2 s 0 4 0 2 ~580~5
- 2 - D 21 AND2 s 0 4 0 1 ~4341~1
- 2 - D 31 AND2 s 0 4 0 1 ~4341~2
- 2 - D 25 AND2 s 0 4 0 1 ~4341~3
- 4 - D 34 AND2 s 0 4 0 1 ~4341~4
- 3 - D 21 AND2 s 0 4 0 1 ~4341~5
- 4 - D 26 AND2 3 0 0 19 :4717
- 5 - D 36 OR2 0 3 0 1 :4720
- 7 - D 21 AND2 0 4 0 18 :4722
- 1 - D 26 AND2 3 0 0 19 :4727
- 3 - D 26 AND2 3 0 0 19 :4737
- 8 - D 36 AND2 0 2 0 1 :4741
- 6 - D 36 OR2 0 4 0 1 :4742
- 5 - D 26 AND2 3 0 0 19 :4747
- 4 - D 31 OR2 0 4 0 18 :4751
- 2 - D 36 OR2 0 3 0 1 :4756
- 3 - D 36 OR2 0 3 0 1 :4759
- 4 - D 36 OR2 0 4 0 1 :4762
- 5 - D 27 OR2 0 3 0 1 :4771
- 7 - D 27 OR2 0 3 0 1 :4774
- 8 - D 27 OR2 0 4 0 1 :4777
- 2 - D 27 OR2 0 3 0 1 :4786
- 3 - D 27 OR2 0 3 0 1 :4789
- 4 - D 27 OR2 0 4 0 1 :4792
- 4 - D 21 OR2 0 3 0 1 :4801
- 5 - D 21 OR2 0 3 0 1 :4804
- 8 - D 21 OR2 0 4 0 1 :4807
- 5 - D 22 OR2 0 3 0 1 :4816
- 6 - D 22 OR2 0 3 0 1 :4819
- 7 - D 22 OR2 0 4 0 1 :4822
- 2 - D 22 OR2 0 3 0 1 :4831
- 3 - D 22 OR2 0 3 0 1 :4834
- 4 - D 22 OR2 0 4 0 1 :4837
- 6 - D 35 OR2 0 3 0 1 :4846
- 7 - D 35 OR2 0 3 0 1 :4849
- 8 - D 35 OR2 0 4 0 1 :4852
- 7 - D 34 OR2 0 3 0 2 :4865
- 2 - D 35 OR2 0 4 0 1 :4866
- 3 - D 35 OR2 0 4 0 1 :4867
- 5 - D 31 OR2 0 4 0 18 :4868
- 3 - D 31 OR2 0 4 0 1 :4881
- 4 - D 35 OR2 0 4 0 1 :4882
- 6 - D 31 OR2 s 0 4 0 1 ~4900~1
- 8 - D 20 OR2 s 0 4 0 1 ~4900~2
- 6 - D 20 OR2 s 0 4 0 1 ~4915~1
- 7 - D 20 OR2 s 0 4 0 1 ~4915~2
- 4 - D 20 OR2 s 0 4 0 1 ~4930~1
- 5 - D 20 OR2 s 0 4 0 1 ~4930~2
- 7 - D 26 OR2 s 0 4 0 1 ~4945~1
- 6 - D 26 OR2 s 0 4 0 1 ~4945~2
- 6 - D 25 OR2 s 0 4 0 1 ~4960~1
- 8 - D 25 OR2 s 0 4 0 1 ~4960~2
- 6 - D 34 OR2 s 0 4 0 1 ~4975~1
- 8 - D 34 OR2 s 0 4 0 1 ~4975~2
- 2 - D 26 OR2 s 0 4 0 1 ~4990~1
- 8 - D 26 OR2 s 0 4 0 1 ~4990~2
- 8 - D 31 OR2 s 0 4 0 1 ~5005~1
- 3 - D 34 OR2 s 0 4 0 1 ~5005~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\three\horse\ledt18.rpt
ledt18
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 32/144( 22%) 0/ 72( 0%) 12/ 72( 16%) 0/16( 0%) 11/16( 68%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\three\horse\ledt18.rpt
ledt18
** CLOCK SIGNALS **
Type Fan-out Name
DFF 18 f_scan1
INPUT 4 clk
Device-Specific Information: d:\three\horse\ledt18.rpt
ledt18
** EQUATIONS **
clk : INPUT;
mode0 : INPUT;
mode1 : INPUT;
mode2 : INPUT;
-- Node name is ':45' = 'd_ff0'
-- Equation name is 'd_ff0', location is LC1_D33, type is buried.
d_ff0 = DFFE(!d_ff0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':44' = 'd_ff1'
-- Equation name is 'd_ff1', location is LC2_D33, type is buried.
d_ff1 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = d_ff0 & !d_ff1
# !d_ff0 & d_ff1;
-- Node name is ':43' = 'd_ff2'
-- Equation name is 'd_ff2', location is LC3_D33, type is buried.
d_ff2 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !d_ff0 & d_ff2
# !d_ff1 & d_ff2
# d_ff0 & d_ff1 & !d_ff2;
-- Node name is ':23' = 'f_scan1'
-- Equation name is 'f_scan1', location is LC5_D33, type is buried.
f_scan1 = DFFE(!d_ff2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':41' = 'f0'
-- Equation name is 'f0', location is LC2_D34, type is buried.
f0 = DFFE( _EQ003, f_scan1, VCC, VCC, VCC);
_EQ003 = _LC3_D34 & !_LC5_D26
# f1 & _LC4_D31;
-- Node name is ':40' = 'f1'
-- Equation name is 'f1', location is LC1_D34, type is buried.
f1 = DFFE( _EQ004, f_scan1, VCC, VCC, VCC);
_EQ004 = !_LC5_D26 & _LC8_D26
# f2 & _LC4_D31;
-- Node name is ':39' = 'f2'
-- Equation name is 'f2', location is LC5_D34, type is buried.
f2 = DFFE( _EQ005, f_scan1, VCC, VCC, VCC);
_EQ005 = !_LC5_D26 & _LC8_D34
# f3 & _LC4_D31;
-- Node name is ':38' = 'f3'
-- Equation name is 'f3', location is LC4_D25, type is buried.
f3 = DFFE( _EQ006, f_scan1, VCC, VCC, VCC);
_EQ006 = !_LC5_D26 & _LC8_D25
# f4 & _LC4_D31;
-- Node name is ':37' = 'f4'
-- Equation name is 'f4', location is LC5_D25, type is buried.
f4 = DFFE( _EQ007, f_scan1, VCC, VCC, VCC);
_EQ007 = !_LC5_D26 & _LC6_D26
# f5 & _LC4_D31;
-- Node name is ':36' = 'f5'
-- Equation name is 'f5', location is LC3_D20, type is buried.
f5 = DFFE( _EQ008, f_scan1, VCC, VCC, VCC);
_EQ008 = _LC5_D20 & !_LC5_D26
# f6 & _LC4_D31;
-- Node name is ':35' = 'f6'
-- Equation name is 'f6', location is LC2_D20, type is buried.
f6 = DFFE( _EQ009, f_scan1, VCC, VCC, VCC);
_EQ009 = !_LC5_D26 & _LC7_D20
# f7 & _LC4_D31;
-- Node name is ':34' = 'f7'
-- Equation name is 'f7', location is LC1_D20, type is buried.
f7 = DFFE( _EQ010, f_scan1, VCC, VCC, VCC);
_EQ010 = !_LC5_D26 & _LC8_D20
# f8 & _LC4_D31;
-- Node name is ':33' = 'f8'
-- Equation name is 'f8', location is LC7_D31, type is buried.
f8 = DFFE( _EQ011, f_scan1, VCC, VCC, VCC);
_EQ011 = _LC4_D35 & !_LC5_D26
# f9 & _LC4_D31;
-- Node name is ':32' = 'f9'
-- Equation name is 'f9', location is LC5_D35, type is buried.
f9 = DFFE( _EQ012, f_scan1, VCC, VCC, VCC);
_EQ012 = _LC3_D35 & !_LC5_D26
# f10 & _LC4_D31;
-- Node name is ':31' = 'f10'
-- Equation name is 'f10', location is LC1_D35, type is buried.
f10 = DFFE( _EQ013, f_scan1, VCC, VCC, VCC);
_EQ013 = !_LC5_D26 & _LC8_D35
# f11 & _LC4_D31;
-- Node name is ':30' = 'f11'
-- Equation name is 'f11', location is LC8_D22, type is buried.
f11 = DFFE( _EQ014, f_scan1, VCC, VCC, VCC);
_EQ014 = _LC4_D22 & !_LC5_D26
# f12 & _LC4_D31;
-- Node name is ':29' = 'f12'
-- Equation name is 'f12', location is LC1_D22, type is buried.
f12 = DFFE( _EQ015, f_scan1, VCC, VCC, VCC);
_EQ015 = !_LC5_D26 & _LC7_D22
# f13 & _LC4_D31;
-- Node name is ':28' = 'f13'
-- Equation name is 'f13', location is LC1_D21, type is buried.
f13 = DFFE( _EQ016, f_scan1, VCC, VCC, VCC);
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