📄 ledrun18.rpt
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_LC7_E12 = LCELL( _EQ050);
_EQ050 = !_LC2_F17 & _LC6_E12
# _LC2_F17 & _LC8_E14;
-- Node name is '|LEDT18:16|:4807'
-- Equation name is '_LC8_E12', type is buried
_LC8_E12 = LCELL( _EQ051);
_EQ051 = !_LC4_F17 & _LC7_E12
# _LC2_E12 & _LC8_E14;
-- Node name is '|LEDT18:16|:4816'
-- Equation name is '_LC5_E14', type is buried
_LC5_E14 = LCELL( _EQ052);
_EQ052 = _LC1_E12 & _LC3_F17
# _LC1_E14;
-- Node name is '|LEDT18:16|:4819'
-- Equation name is '_LC6_E14', type is buried
_LC6_E14 = LCELL( _EQ053);
_EQ053 = !_LC2_F17 & _LC5_E14
# _LC1_A14 & _LC2_F17;
-- Node name is '|LEDT18:16|:4822'
-- Equation name is '_LC7_E14', type is buried
_LC7_E14 = LCELL( _EQ054);
_EQ054 = !_LC4_F17 & _LC6_E14
# _LC1_A14 & _LC2_E12;
-- Node name is '|LEDT18:16|:4831'
-- Equation name is '_LC6_A14', type is buried
_LC6_A14 = LCELL( _EQ055);
_EQ055 = _LC3_F17 & _LC8_E14
# _LC1_E14;
-- Node name is '|LEDT18:16|:4834'
-- Equation name is '_LC7_A14', type is buried
_LC7_A14 = LCELL( _EQ056);
_EQ056 = !_LC2_F17 & _LC6_A14
# _LC2_A14 & _LC2_F17;
-- Node name is '|LEDT18:16|:4837'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = LCELL( _EQ057);
_EQ057 = !_LC4_F17 & _LC7_A14
# _LC2_A14 & _LC2_E12;
-- Node name is '|LEDT18:16|:4846'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = LCELL( _EQ058);
_EQ058 = _LC1_A14 & _LC3_F17
# _LC1_E14;
-- Node name is '|LEDT18:16|:4849'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = LCELL( _EQ059);
_EQ059 = !_LC2_F17 & _LC3_A14
# _LC2_F17 & _LC3_E15;
-- Node name is '|LEDT18:16|:4852'
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = LCELL( _EQ060);
_EQ060 = _LC4_A14 & !_LC4_F17
# _LC2_E12 & _LC3_E15;
-- Node name is '|LEDT18:16|:4865'
-- Equation name is '_LC3_E9', type is buried
_LC3_E9 = LCELL( _EQ061);
_EQ061 = !_LC2_E13 & _LC2_F17
# _LC2_F17 & !_LC5_E23;
-- Node name is '|LEDT18:16|:4866'
-- Equation name is '_LC8_E17', type is buried
_LC8_E17 = LCELL( _EQ062);
_EQ062 = _LC2_A14 & !_LC2_F17 & _LC3_F17
# _LC1_E14 & !_LC2_F17;
-- Node name is '|LEDT18:16|:4867'
-- Equation name is '_LC5_E17', type is buried
_LC5_E17 = LCELL( _EQ063);
_EQ063 = !_LC4_F17 & _LC8_E17
# _LC3_E9 & !_LC4_F17
# _LC2_E12;
-- Node name is '|LEDT18:16|:4868'
-- Equation name is '_LC2_E12', type is buried
_LC2_E12 = LCELL( _EQ064);
_EQ064 = _LC4_E12 & _LC4_F17
# _LC4_F17 & _LC5_E12
# _LC4_F17 & _LC8_E9;
-- Node name is '|LEDT18:16|:4881'
-- Equation name is '_LC7_E17', type is buried
_LC7_E17 = LCELL( _EQ065);
_EQ065 = !_LC2_F17 & _LC3_E15 & _LC3_F17
# _LC1_E14 & !_LC2_F17;
-- Node name is '|LEDT18:16|:4882'
-- Equation name is '_LC3_E17', type is buried
_LC3_E17 = LCELL( _EQ066);
_EQ066 = _LC3_E9 & !_LC4_F17
# !_LC4_F17 & _LC7_E17
# _LC2_E12;
-- Node name is '|LEDT18:16|~4900~1'
-- Equation name is '_LC4_E17', type is buried
-- synthesized logic cell
_LC4_E17 = LCELL( _EQ067);
_EQ067 = _LC3_F17 & _LC6_E15
# _LC2_F17 & _LC6_E15
# _LC1_E14 & !_LC2_F17;
-- Node name is '|LEDT18:16|~4900~2'
-- Equation name is '_LC6_E17', type is buried
-- synthesized logic cell
_LC6_E17 = LCELL( _EQ068);
_EQ068 = _LC4_E17 & !_LC4_F17
# _LC2_E12 & _LC6_E15;
-- Node name is '|LEDT18:16|~4915~1'
-- Equation name is '_LC2_E17', type is buried
-- synthesized logic cell
_LC2_E17 = LCELL( _EQ069);
_EQ069 = _LC1_E14 & !_LC2_F17
# _LC1_E17 & _LC3_F17
# _LC1_E17 & _LC2_F17;
-- Node name is '|LEDT18:16|~4915~2'
-- Equation name is '_LC8_E19', type is buried
-- synthesized logic cell
_LC8_E19 = LCELL( _EQ070);
_EQ070 = _LC2_E17 & !_LC4_F17
# _LC1_E17 & _LC2_E12;
-- Node name is '|LEDT18:16|~4930~1'
-- Equation name is '_LC6_E19', type is buried
-- synthesized logic cell
_LC6_E19 = LCELL( _EQ071);
_EQ071 = _LC1_E14 & !_LC2_F17
# _LC2_E19 & _LC3_F17
# _LC2_E19 & _LC2_F17;
-- Node name is '|LEDT18:16|~4930~2'
-- Equation name is '_LC7_E19', type is buried
-- synthesized logic cell
_LC7_E19 = LCELL( _EQ072);
_EQ072 = !_LC4_F17 & _LC6_E19
# _LC2_E12 & _LC2_E19;
-- Node name is '|LEDT18:16|~4945~1'
-- Equation name is '_LC4_E19', type is buried
-- synthesized logic cell
_LC4_E19 = LCELL( _EQ073);
_EQ073 = _LC1_E14 & !_LC2_F17
# _LC3_E19 & _LC3_F17
# _LC2_F17 & _LC3_E19;
-- Node name is '|LEDT18:16|~4945~2'
-- Equation name is '_LC5_E19', type is buried
-- synthesized logic cell
_LC5_E19 = LCELL( _EQ074);
_EQ074 = _LC4_E19 & !_LC4_F17
# _LC2_E12 & _LC3_E19;
-- Node name is '|LEDT18:16|~4960~1'
-- Equation name is '_LC7_E21', type is buried
-- synthesized logic cell
_LC7_E21 = LCELL( _EQ075);
_EQ075 = _LC1_E14 & !_LC2_F17
# _LC1_E19 & _LC3_F17
# _LC1_E19 & _LC2_F17;
-- Node name is '|LEDT18:16|~4960~2'
-- Equation name is '_LC8_E21', type is buried
-- synthesized logic cell
_LC8_E21 = LCELL( _EQ076);
_EQ076 = !_LC4_F17 & _LC7_E21
# _LC1_E19 & _LC2_E12;
-- Node name is '|LEDT18:16|~4975~1'
-- Equation name is '_LC4_E21', type is buried
-- synthesized logic cell
_LC4_E21 = LCELL( _EQ077);
_EQ077 = _LC1_E14 & !_LC2_F17
# _LC1_E21 & _LC3_F17
# _LC1_E21 & _LC2_F17;
-- Node name is '|LEDT18:16|~4975~2'
-- Equation name is '_LC6_E21', type is buried
-- synthesized logic cell
_LC6_E21 = LCELL( _EQ078);
_EQ078 = _LC4_E21 & !_LC4_F17
# _LC1_E21 & _LC2_E12;
-- Node name is '|LEDT18:16|~4990~1'
-- Equation name is '_LC2_E21', type is buried
-- synthesized logic cell
_LC2_E21 = LCELL( _EQ079);
_EQ079 = _LC1_E14 & !_LC2_F17
# _LC3_F17 & _LC5_E21
# _LC2_F17 & _LC5_E21;
-- Node name is '|LEDT18:16|~4990~2'
-- Equation name is '_LC3_E21', type is buried
-- synthesized logic cell
_LC3_E21 = LCELL( _EQ080);
_EQ080 = _LC2_E21 & !_LC4_F17
# _LC2_E12 & _LC5_E21;
-- Node name is '|LEDT18:16|~5005~1'
-- Equation name is '_LC8_E13', type is buried
-- synthesized logic cell
_LC8_E13 = LCELL( _EQ081);
_EQ081 = _LC1_E14 & !_LC2_F17
# _LC1_E23 & _LC3_F17
# _LC1_E23 & _LC2_F17;
-- Node name is '|LEDT18:16|~5005~2'
-- Equation name is '_LC5_E9', type is buried
-- synthesized logic cell
_LC5_E9 = LCELL( _EQ082);
_EQ082 = !_LC4_F17 & _LC8_E13
# _LC1_E23 & _LC2_E12;
Project Information d:\horse\ledrun18.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:06
-------------------------- --------
Total Time 00:00:08
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,533K
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