📄 ledrun18.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\horse\ledrun18.rpt
ledrun18
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
68 - - - 24 OUTPUT 0 1 0 0 LED9
69 - - - 23 OUTPUT 0 1 0 0 LED10
70 - - - 22 OUTPUT 0 1 0 0 LED11
71 - - - 21 OUTPUT 0 1 0 0 LED12
73 - - - 20 OUTPUT 0 1 0 0 LED13
74 - - - 20 OUTPUT 0 1 0 0 LED14
75 - - - 19 OUTPUT 0 1 0 0 LED15
83 - - - 17 OUTPUT 0 1 0 0 LED16
85 - - - 16 OUTPUT 0 1 0 0 LED17
86 - - - 15 OUTPUT 0 1 0 0 LED18
87 - - - 14 OUTPUT 0 1 0 0 LED19
88 - - - 14 OUTPUT 0 1 0 0 LED20
89 - - - 13 OUTPUT 0 1 0 0 LED21
90 - - - 12 OUTPUT 0 1 0 0 LED22
92 - - - 11 OUTPUT 0 1 0 0 LED23
93 - - - 10 OUTPUT 0 1 0 0 LED24
173 - - - 13 OUTPUT 0 1 0 0 LED25
174 - - - 14 OUTPUT 0 1 0 0 LED26
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\horse\ledrun18.rpt
ledrun18
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - E 15 DFFE + 0 1 0 18 |LEDT18:16|f_scan1 (|LEDT18:16|:23)
- 2 - E 13 DFFE 0 5 1 5 |LEDT18:16|f17 (|LEDT18:16|:24)
- 1 - E 13 DFFE 0 5 1 6 |LEDT18:16|f16 (|LEDT18:16|:25)
- 4 - E 09 DFFE 0 5 1 6 |LEDT18:16|f15 (|LEDT18:16|:26)
- 1 - E 11 DFFE 0 5 1 6 |LEDT18:16|f14 (|LEDT18:16|:27)
- 1 - E 12 DFFE 0 5 1 6 |LEDT18:16|f13 (|LEDT18:16|:28)
- 8 - E 14 DFFE 0 5 1 6 |LEDT18:16|f12 (|LEDT18:16|:29)
- 1 - A 14 DFFE 0 5 1 6 |LEDT18:16|f11 (|LEDT18:16|:30)
- 2 - A 14 DFFE 0 5 1 6 |LEDT18:16|f10 (|LEDT18:16|:31)
- 3 - E 15 DFFE 0 5 1 6 |LEDT18:16|f9 (|LEDT18:16|:32)
- 6 - E 15 DFFE 0 5 1 5 |LEDT18:16|f8 (|LEDT18:16|:33)
- 1 - E 17 DFFE 0 5 1 5 |LEDT18:16|f7 (|LEDT18:16|:34)
- 2 - E 19 DFFE 0 5 1 5 |LEDT18:16|f6 (|LEDT18:16|:35)
- 3 - E 19 DFFE 0 5 1 5 |LEDT18:16|f5 (|LEDT18:16|:36)
- 1 - E 19 DFFE 0 5 1 5 |LEDT18:16|f4 (|LEDT18:16|:37)
- 1 - E 21 DFFE 0 5 1 5 |LEDT18:16|f3 (|LEDT18:16|:38)
- 5 - E 21 DFFE 0 5 1 5 |LEDT18:16|f2 (|LEDT18:16|:39)
- 1 - E 23 DFFE 0 5 1 5 |LEDT18:16|f1 (|LEDT18:16|:40)
- 5 - E 23 DFFE 0 5 1 4 |LEDT18:16|f0 (|LEDT18:16|:41)
- 4 - E 15 DFFE + 0 2 0 1 |LEDT18:16|d_ff2 (|LEDT18:16|:43)
- 2 - E 15 DFFE + 0 1 0 1 |LEDT18:16|d_ff1 (|LEDT18:16|:44)
- 1 - E 15 DFFE + 0 0 0 2 |LEDT18:16|d_ff0 (|LEDT18:16|:45)
- 4 - E 12 OR2 s 0 4 0 2 |LEDT18:16|~580~1
- 5 - E 12 OR2 s 0 4 0 2 |LEDT18:16|~580~2
- 6 - E 09 OR2 s 0 4 0 1 |LEDT18:16|~580~3
- 7 - E 09 OR2 s 0 4 0 1 |LEDT18:16|~580~4
- 8 - E 09 OR2 s 0 4 0 2 |LEDT18:16|~580~5
- 2 - E 14 AND2 s 0 4 0 1 |LEDT18:16|~4341~1
- 3 - E 14 AND2 s 0 4 0 1 |LEDT18:16|~4341~2
- 1 - E 09 AND2 s 0 4 0 1 |LEDT18:16|~4341~3
- 2 - E 09 AND2 s 0 4 0 1 |LEDT18:16|~4341~4
- 4 - E 14 AND2 s 0 4 0 1 |LEDT18:16|~4341~5
- 3 - F 17 AND2 3 0 0 19 |LEDT18:16|:4717
- 5 - E 13 OR2 0 3 0 1 |LEDT18:16|:4720
- 1 - E 14 AND2 0 4 0 18 |LEDT18:16|:4722
- 2 - F 17 AND2 3 0 0 19 |LEDT18:16|:4727
- 4 - F 17 AND2 3 0 0 19 |LEDT18:16|:4737
- 7 - E 13 AND2 0 2 0 1 |LEDT18:16|:4741
- 6 - E 13 OR2 0 4 0 1 |LEDT18:16|:4742
- 1 - F 17 AND2 3 0 0 19 |LEDT18:16|:4747
- 3 - E 12 OR2 0 4 0 18 |LEDT18:16|:4751
- 7 - E 11 OR2 0 3 0 1 |LEDT18:16|:4756
- 8 - E 11 OR2 0 3 0 1 |LEDT18:16|:4759
- 4 - E 11 OR2 0 4 0 1 |LEDT18:16|:4762
- 3 - E 13 OR2 0 3 0 1 |LEDT18:16|:4771
- 4 - E 13 OR2 0 3 0 1 |LEDT18:16|:4774
- 2 - E 11 OR2 0 4 0 1 |LEDT18:16|:4777
- 3 - E 11 OR2 0 3 0 1 |LEDT18:16|:4786
- 5 - E 11 OR2 0 3 0 1 |LEDT18:16|:4789
- 6 - E 11 OR2 0 4 0 1 |LEDT18:16|:4792
- 6 - E 12 OR2 0 3 0 1 |LEDT18:16|:4801
- 7 - E 12 OR2 0 3 0 1 |LEDT18:16|:4804
- 8 - E 12 OR2 0 4 0 1 |LEDT18:16|:4807
- 5 - E 14 OR2 0 3 0 1 |LEDT18:16|:4816
- 6 - E 14 OR2 0 3 0 1 |LEDT18:16|:4819
- 7 - E 14 OR2 0 4 0 1 |LEDT18:16|:4822
- 6 - A 14 OR2 0 3 0 1 |LEDT18:16|:4831
- 7 - A 14 OR2 0 3 0 1 |LEDT18:16|:4834
- 8 - A 14 OR2 0 4 0 1 |LEDT18:16|:4837
- 3 - A 14 OR2 0 3 0 1 |LEDT18:16|:4846
- 4 - A 14 OR2 0 3 0 1 |LEDT18:16|:4849
- 5 - A 14 OR2 0 4 0 1 |LEDT18:16|:4852
- 3 - E 09 OR2 0 3 0 2 |LEDT18:16|:4865
- 8 - E 17 OR2 0 4 0 1 |LEDT18:16|:4866
- 5 - E 17 OR2 0 4 0 1 |LEDT18:16|:4867
- 2 - E 12 OR2 0 4 0 18 |LEDT18:16|:4868
- 7 - E 17 OR2 0 4 0 1 |LEDT18:16|:4881
- 3 - E 17 OR2 0 4 0 1 |LEDT18:16|:4882
- 4 - E 17 OR2 s 0 4 0 1 |LEDT18:16|~4900~1
- 6 - E 17 OR2 s 0 4 0 1 |LEDT18:16|~4900~2
- 2 - E 17 OR2 s 0 4 0 1 |LEDT18:16|~4915~1
- 8 - E 19 OR2 s 0 4 0 1 |LEDT18:16|~4915~2
- 6 - E 19 OR2 s 0 4 0 1 |LEDT18:16|~4930~1
- 7 - E 19 OR2 s 0 4 0 1 |LEDT18:16|~4930~2
- 4 - E 19 OR2 s 0 4 0 1 |LEDT18:16|~4945~1
- 5 - E 19 OR2 s 0 4 0 1 |LEDT18:16|~4945~2
- 7 - E 21 OR2 s 0 4 0 1 |LEDT18:16|~4960~1
- 8 - E 21 OR2 s 0 4 0 1 |LEDT18:16|~4960~2
- 4 - E 21 OR2 s 0 4 0 1 |LEDT18:16|~4975~1
- 6 - E 21 OR2 s 0 4 0 1 |LEDT18:16|~4975~2
- 2 - E 21 OR2 s 0 4 0 1 |LEDT18:16|~4990~1
- 3 - E 21 OR2 s 0 4 0 1 |LEDT18:16|~4990~2
- 8 - E 13 OR2 s 0 4 0 1 |LEDT18:16|~5005~1
- 5 - E 09 OR2 s 0 4 0 1 |LEDT18:16|~5005~2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\horse\ledrun18.rpt
ledrun18
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/144( 4%) 4/ 72( 5%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 35/144( 24%) 10/ 72( 13%) 0/ 72( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
F: 3/144( 2%) 0/ 72( 0%) 0/ 72( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
14: 4/24( 16%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\horse\ledrun18.rpt
ledrun18
** CLOCK SIGNALS **
Type Fan-out Name
DFF 18 |LEDT18:16|f_scan1
INPUT 4 CLK
Device-Specific Information: d:\horse\ledrun18.rpt
ledrun18
** EQUATIONS **
CLK : INPUT;
MODE0 : INPUT;
MODE1 : INPUT;
MODE2 : INPUT;
SW1 : INPUT;
SW2 : INPUT;
SW3 : INPUT;
SW4 : INPUT;
SW5 : INPUT;
-- Node name is 'LED9'
-- Equation name is 'LED9', type is output
LED9 = _LC5_E23;
-- Node name is 'LED10'
-- Equation name is 'LED10', type is output
LED10 = _LC1_E23;
-- Node name is 'LED11'
-- Equation name is 'LED11', type is output
LED11 = _LC5_E21;
-- Node name is 'LED12'
-- Equation name is 'LED12', type is output
LED12 = _LC1_E21;
-- Node name is 'LED13'
-- Equation name is 'LED13', type is output
LED13 = _LC1_E19;
-- Node name is 'LED14'
-- Equation name is 'LED14', type is output
LED14 = _LC3_E19;
-- Node name is 'LED15'
-- Equation name is 'LED15', type is output
LED15 = _LC2_E19;
-- Node name is 'LED16'
-- Equation name is 'LED16', type is output
LED16 = _LC1_E17;
-- Node name is 'LED17'
-- Equation name is 'LED17', type is output
LED17 = _LC6_E15;
-- Node name is 'LED18'
-- Equation name is 'LED18', type is output
LED18 = _LC3_E15;
-- Node name is 'LED19'
-- Equation name is 'LED19', type is output
LED19 = _LC2_A14;
-- Node name is 'LED20'
-- Equation name is 'LED20', type is output
LED20 = _LC1_A14;
-- Node name is 'LED21'
-- Equation name is 'LED21', type is output
LED21 = _LC8_E14;
-- Node name is 'LED22'
-- Equation name is 'LED22', type is output
LED22 = _LC1_E12;
-- Node name is 'LED23'
-- Equation name is 'LED23', type is output
LED23 = _LC1_E11;
-- Node name is 'LED24'
-- Equation name is 'LED24', type is output
LED24 = _LC4_E9;
-- Node name is 'LED25'
-- Equation name is 'LED25', type is output
LED25 = _LC1_E13;
-- Node name is 'LED26'
-- Equation name is 'LED26', type is output
LED26 = _LC2_E13;
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