de2_default.tan.summary

噪生消除的VRILOG实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.650 ns
From           : KEY[0]
To             : w2[17]
From Clock     : --
To Clock       : CLOCK_27
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.609 ns
From           : I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[2]
To             : I2C_SCLK
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.612 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.740 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_27'
Slack          : 0.500 ns
Required Time  : 27.00 MHz ( period = 37.037 ns )
Actual Time    : N/A
From           : AUDIO_DAC_ADC:u4|LRCK_1X
To             : state.0001
From Clock     : VGA_Audio_PLL:p1|altpll:altpll_component|_clk1
To Clock       : CLOCK_27
Failed Paths   : 0

Type           : Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk1'
Slack          : 8.568 ns
Required Time  : 18.00 MHz ( period = 55.555 ns )
Actual Time    : N/A
From           : audio_outL[0]
To             : AUDIO_DAC_ADC:u4|AUD_outL[0]
From Clock     : CLOCK_27
To Clock       : VGA_Audio_PLL:p1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 143.18 MHz ( period = 6.984 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : N/A
Required Time  : None
Actual Time    : 167.11 MHz ( period = 5.984 ns )
From           : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3]
To             : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[1]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk1'
Slack          : 0.391 ns
Required Time  : 18.00 MHz ( period = 55.555 ns )
Actual Time    : N/A
From           : AUDIO_DAC_ADC:u4|AUD_inR[6]
To             : AUDIO_DAC_ADC:u4|AUD_inR[6]
From Clock     : VGA_Audio_PLL:p1|altpll:altpll_component|_clk1
To Clock       : VGA_Audio_PLL:p1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_27'
Slack          : 0.391 ns
Required Time  : 27.00 MHz ( period = 37.037 ns )
Actual Time    : N/A
From           : we
To             : we
From Clock     : CLOCK_27
To Clock       : CLOCK_27
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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