de2_default.fit.qmsg

噪生消除的VRILOG实现

{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "32 Embedded multiplier block " "Extra Info: Packed 32 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "17 " "Extra Info: Created 17 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll clk\[1\] AUD_XCK " "Warning: PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" output port clk\[1\] feeds output pin \"AUD_XCK\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "VGA_Audio_PLL.v" "" { Text "C:/DE2/NoiseCancel/VGA_Audio_PLL.v" 89 -1 0 } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 327 -1 0 } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 293 -1 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll clk\[2\] VGA_CLK " "Warning: PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" output port clk\[2\] feeds output pin \"VGA_CLK\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "VGA_Audio_PLL.v" "" { Text "C:/DE2/NoiseCancel/VGA_Audio_PLL.v" 89 -1 0 } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 327 -1 0 } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 270 -1 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}