📄 de2_default.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_27 register AUDIO_DAC_ADC:u4\|LRCK_1X register state.0001 500 ps " "Info: Slack time is 500 ps for clock \"CLOCK_27\" between source register \"AUDIO_DAC_ADC:u4\|LRCK_1X\" and destination register \"state.0001\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.182 ns + Largest register register " "Info: + Largest register to register requirement is 2.182 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.384 ns + " "Info: + Setup relationship between source and destination is 2.384 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 18.518 ns " "Info: + Latch edge is 18.518 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_27 37.037 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"CLOCK_27\" is 37.037 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 16.134 ns " "Info: - Launch edge is 16.134 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 55.555 ns -2.384 ns 50 " "Info: Clock period of Source clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" is 55.555 ns with offset of -2.384 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.012 ns + Largest " "Info: + Largest clock skew is 0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_27 destination 2.630 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_27\" to destination register is 2.630 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CLOCK_27 1 CLK PIN_D13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 3; CLK Node = 'CLOCK_27'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_27 } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 178 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.092 ns CLOCK_27~clkctrl 2 COMB CLKCTRL_G9 148 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.092 ns; Loc. = CLKCTRL_G9; Fanout = 148; COMB Node = 'CLOCK_27~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.113 ns" { CLOCK_27 CLOCK_27~clkctrl } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 178 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.537 ns) 2.630 ns state.0001 3 REG LCFF_X51_Y14_N25 2 " "Info: 3: + IC(1.001 ns) + CELL(0.537 ns) = 2.630 ns; Loc. = LCFF_X51_Y14_N25; Fanout = 2; REG Node = 'state.0001'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.538 ns" { CLOCK_27~clkctrl state.0001 } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 359 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 57.64 % ) " "Info: Total cell delay = 1.516 ns ( 57.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.114 ns ( 42.36 % ) " "Info: Total interconnect delay = 1.114 ns ( 42.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.630 ns" { CLOCK_27 CLOCK_27~clkctrl state.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.630 ns" { CLOCK_27 CLOCK_27~combout CLOCK_27~clkctrl state.0001 } { 0.000ns 0.000ns 0.113ns 1.001ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 source 2.618 ns - Longest register " "Info: - Longest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" to source register is 2.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G11 15 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G11; Fanout = 15; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.537 ns) 2.618 ns AUDIO_DAC_ADC:u4\|LRCK_1X 3 REG LCFF_X37_Y15_N17 10 " "Info: 3: + IC(1.006 ns) + CELL(0.537 ns) = 2.618 ns; Loc. = LCFF_X37_Y15_N17; Fanout = 10; REG Node = 'AUDIO_DAC_ADC:u4\|LRCK_1X'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.543 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } "NODE_NAME" } } { "AUDIO_DAC_ADC.v" "" { Text "C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v" 87 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.51 % ) " "Info: Total cell delay = 0.537 ns ( 20.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.081 ns ( 79.49 % ) " "Info: Total interconnect delay = 2.081 ns ( 79.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.618 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.618 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } { 0.000ns 1.075ns 1.006ns } { 0.000ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.630 ns" { CLOCK_27 CLOCK_27~clkctrl state.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.630 ns" { CLOCK_27 CLOCK_27~combout CLOCK_27~clkctrl state.0001 } { 0.000ns 0.000ns 0.113ns 1.001ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.618 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.618 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } { 0.000ns 1.075ns 1.006ns } { 0.000ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "AUDIO_DAC_ADC.v" "" { Text "C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v" 87 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 359 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.630 ns" { CLOCK_27 CLOCK_27~clkctrl state.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.630 ns" { CLOCK_27 CLOCK_27~combout CLOCK_27~clkctrl state.0001 } { 0.000ns 0.000ns 0.113ns 1.001ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.618 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.618 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } { 0.000ns 1.075ns 1.006ns } { 0.000ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.682 ns - Longest register register " "Info: - Longest register to register delay is 1.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AUDIO_DAC_ADC:u4\|LRCK_1X 1 REG LCFF_X37_Y15_N17 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y15_N17; Fanout = 10; REG Node = 'AUDIO_DAC_ADC:u4\|LRCK_1X'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUDIO_DAC_ADC:u4|LRCK_1X } "NODE_NAME" } } { "AUDIO_DAC_ADC.v" "" { Text "C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v" 87 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.448 ns) + CELL(0.150 ns) 1.598 ns state~110 2 COMB LCCOMB_X51_Y14_N24 1 " "Info: 2: + IC(1.448 ns) + CELL(0.150 ns) = 1.598 ns; Loc. = LCCOMB_X51_Y14_N24; Fanout = 1; COMB Node = 'state~110'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.598 ns" { AUDIO_DAC_ADC:u4|LRCK_1X state~110 } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 359 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.682 ns state.0001 3 REG LCFF_X51_Y14_N25 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.682 ns; Loc. = LCFF_X51_Y14_N25; Fanout = 2; REG Node = 'state.0001'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { state~110 state.0001 } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 359 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 13.91 % ) " "Info: Total cell delay = 0.234 ns ( 13.91 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.448 ns ( 86.09 % ) " "Info: Total interconnect delay = 1.448 ns ( 86.09 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.682 ns" { AUDIO_DAC_ADC:u4|LRCK_1X state~110 state.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.682 ns" { AUDIO_DAC_ADC:u4|LRCK_1X state~110 state.0001 } { 0.000ns 1.448ns 0.000ns } { 0.000ns 0.150ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.630 ns" { CLOCK_27 CLOCK_27~clkctrl state.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.630 ns" { CLOCK_27 CLOCK_27~combout CLOCK_27~clkctrl state.0001 } { 0.000ns 0.000ns 0.113ns 1.001ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.618 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.618 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } { 0.000ns 1.075ns 1.006ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.682 ns" { AUDIO_DAC_ADC:u4|LRCK_1X state~110 state.0001 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.682 ns" { AUDIO_DAC_ADC:u4|LRCK_1X state~110 state.0001 } { 0.000ns 1.448ns 0.000ns } { 0.000ns 0.150ns 0.084ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\] register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\] 167.11 MHz 5.984 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 167.11 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\]\" (period= 5.984 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.770 ns + Longest register register " "Info: + Longest register to register delay is 5.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\] 1 REG LCFF_X51_Y18_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X51_Y18_N23; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_lqf.tdf" "" { Text "C:/DE2/NoiseCancel/db/cntr_lqf.tdf" 77 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.215 ns) + CELL(0.438 ns) 1.653 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|cmpr_nth:auto_generated\|aeb_int~48 2 COMB LCCOMB_X50_Y18_N30 1 " "Info: 2: + IC(1.215 ns) + CELL(0.438 ns) = 1.653 ns; Loc. = LCCOMB_X50_Y18_N30; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|cmpr_nth:auto_generated\|aeb_int~48'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.653 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~48 } "NODE_NAME" } } { "db/cmpr_nth.tdf" "" { Text "C:/DE2/NoiseCancel/db/cmpr_nth.tdf" 29 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(0.406 ns) 2.748 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|cmpr_nth:auto_generated\|aeb_int~51 3 COMB LCCOMB_X50_Y18_N18 9 " "Info: 3: + IC(0.689 ns) + CELL(0.406 ns) = 2.748 ns; Loc. = LCCOMB_X50_Y18_N18; Fanout = 9; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|cmpr_nth:auto_generated\|aeb_int~51'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.095 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~48 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~51 } "NODE_NAME" } } { "db/cmpr_nth.tdf" "" { Text "C:/DE2/NoiseCancel/db/cmpr_nth.tdf" 29 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.420 ns) 4.151 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|_~2 4 COMB LCCOMB_X49_Y19_N22 7 " "Info: 4: + IC(0.983 ns) + CELL(0.420 ns) = 4.151 ns; Loc. = LCCOMB_X49_Y19_N22; Fanout = 7; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|_~2'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.403 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~51 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|_~2 } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.959 ns) + CELL(0.660 ns) 5.770 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\] 5 REG LCFF_X51_Y18_N23 3 " "Info: 5: + IC(0.959 ns) + CELL(0.660 ns) = 5.770 ns; Loc. = LCFF_X51_Y18_N23; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.619 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|_~2 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_lqf.tdf" "" { Text "C:/DE2/NoiseCancel/db/cntr_lqf.tdf" 77 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.924 ns ( 33.34 % ) " "Info: Total cell delay = 1.924 ns ( 33.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.846 ns ( 66.66 % ) " "Info: Total interconnect delay = 3.846 ns ( 66.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.770 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~48 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~51 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|_~2 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.770 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~48 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~51 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|_~2 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } { 0.000ns 1.215ns 0.689ns 0.983ns 0.959ns } { 0.000ns 0.438ns 0.406ns 0.420ns 0.660ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.676 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 179 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 160 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 160; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 179 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\] 3 REG LCFF_X51_Y18_N23 3 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X51_Y18_N23; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.559 ns" { CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_lqf.tdf" "" { Text "C:/DE2/NoiseCancel/db/cntr_lqf.tdf" 77 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.676 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.676 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.676 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 179 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 160 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 160; COMB Node = 'CLOCK_50~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 179 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\] 3 REG LCFF_X51_Y18_N23 3 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X51_Y18_N23; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_lqf:auto_generated\|safe_q\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.559 ns" { CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "db/cntr_lqf.tdf" "" { Text "C:/DE2/NoiseCancel/db/cntr_lqf.tdf" 77 8 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.676 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.676 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.676 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.676 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.676 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.676 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "db/cntr_lqf.tdf" "" { Text "C:/DE2/NoiseCancel/db/cntr_lqf.tdf" 77 8 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "db/cntr_lqf.tdf" "" { Text "C:/DE2/NoiseCancel/db/cntr_lqf.tdf" 77 8 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.770 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~48 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~51 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|_~2 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.770 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~48 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|cmpr_nth:auto_generated|aeb_int~51 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|_~2 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } { 0.000ns 1.215ns 0.689ns 0.983ns 0.959ns } { 0.000ns 0.438ns 0.406ns 0.420ns 0.660ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.676 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.676 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.676 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.676 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] register sld_hub:sld_hub_inst\|hub_tdo 143.18 MHz 6.984 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 143.18 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 6.984 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.277 ns + Longest register register " "Info: + Longest register to register delay is 3.277 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 1 REG LCFF_X45_Y19_N25 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y19_N25; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.419 ns) 1.440 ns sld_hub:sld_hub_inst\|hub_tdo~759 2 COMB LCCOMB_X46_Y20_N18 1 " "Info: 2: + IC(1.021 ns) + CELL(0.419 ns) = 1.440 ns; Loc. = LCCOMB_X46_Y20_N18; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~759'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo~759 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.244 ns) + CELL(0.419 ns) 2.103 ns sld_hub:sld_hub_inst\|hub_tdo~760 3 COMB LCCOMB_X46_Y20_N24 1 " "Info: 3: + IC(0.244 ns) + CELL(0.419 ns) = 2.103 ns; Loc. = LCCOMB_X46_Y20_N24; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~760'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.663 ns" { sld_hub:sld_hub_inst|hub_tdo~759 sld_hub:sld_hub_inst|hub_tdo~760 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.438 ns) 2.801 ns sld_hub:sld_hub_inst\|hub_tdo~762 4 COMB LCCOMB_X46_Y20_N6 1 " "Info: 4: + IC(0.260 ns) + CELL(0.438 ns) = 2.801 ns; Loc. = LCCOMB_X46_Y20_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~762'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.698 ns" { sld_hub:sld_hub_inst|hub_tdo~760 sld_hub:sld_hub_inst|hub_tdo~762 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135⌨️ 快捷键说明
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