de2_default.tan.qmsg

噪生消除的VRILOG实现

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 register audio_outL\[0\] register AUDIO_DAC_ADC:u4\|AUD_outL\[0\] 8.568 ns " "Info: Slack time is 8.568 ns for clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" between source register \"audio_outL\[0\]\" and destination register \"AUDIO_DAC_ADC:u4\|AUD_outL\[0\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "10.177 ns + Largest register register " "Info: + Largest register to register requirement is 10.177 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "6.875 ns + " "Info: + Setup relationship between source and destination is 6.875 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 6.875 ns " "Info: + Latch edge is 6.875 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 55.555 ns 25.393 ns inverted 50 " "Info: Clock period of Destination clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" is 55.555 ns with inverted offset of 25.393 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_27 37.037 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLOCK_27\" is 37.037 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.516 ns + Largest " "Info: + Largest clock skew is 3.516 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 destination 6.162 ns + Shortest register " "Info: + Shortest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" to destination register is 6.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G11 15 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G11; Fanout = 15; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.787 ns) 2.868 ns AUDIO_DAC_ADC:u4\|LRCK_1X 3 REG LCFF_X37_Y15_N17 10 " "Info: 3: + IC(1.006 ns) + CELL(0.787 ns) = 2.868 ns; Loc. = LCFF_X37_Y15_N17; Fanout = 10; REG Node = 'AUDIO_DAC_ADC:u4\|LRCK_1X'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.793 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X } "NODE_NAME" } } { "AUDIO_DAC_ADC.v" "" { Text "C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.000 ns) 4.604 ns AUDIO_DAC_ADC:u4\|LRCK_1X~clkctrl 4 COMB CLKCTRL_G14 32 " "Info: 4: + IC(1.736 ns) + CELL(0.000 ns) = 4.604 ns; Loc. = CLKCTRL_G14; Fanout = 32; COMB Node = 'AUDIO_DAC_ADC:u4\|LRCK_1X~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.736 ns" { AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl } "NODE_NAME" } } { "AUDIO_DAC_ADC.v" "" { Text "C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 6.162 ns AUDIO_DAC_ADC:u4\|AUD_outL\[0\] 5 REG LCFF_X38_Y15_N1 1 " "Info: 5: + IC(1.021 ns) + CELL(0.537 ns) = 6.162 ns; Loc. = LCFF_X38_Y15_N1; Fanout = 1; REG Node = 'AUDIO_DAC_ADC:u4\|AUD_outL\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.558 ns" { AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } "NODE_NAME" } } { "AUDIO_DAC_ADC.v" "" { Text "C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.324 ns ( 21.49 % ) " "Info: Total cell delay = 1.324 ns ( 21.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.838 ns ( 78.51 % ) " "Info: Total interconnect delay = 4.838 ns ( 78.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.162 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.162 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } { 0.000ns 1.075ns 1.006ns 1.736ns 1.021ns } { 0.000ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_27 source 2.646 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_27\" to source register is 2.646 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CLOCK_27 1 CLK PIN_D13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 3; CLK Node = 'CLOCK_27'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_27 } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 178 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.092 ns CLOCK_27~clkctrl 2 COMB CLKCTRL_G9 148 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.092 ns; Loc. = CLKCTRL_G9; Fanout = 148; COMB Node = 'CLOCK_27~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.113 ns" { CLOCK_27 CLOCK_27~clkctrl } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 178 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.537 ns) 2.646 ns audio_outL\[0\] 3 REG LCFF_X40_Y17_N1 1 " "Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.646 ns; Loc. = LCFF_X40_Y17_N1; Fanout = 1; REG Node = 'audio_outL\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.554 ns" { CLOCK_27~clkctrl audio_outL[0] } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 517 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 57.29 % ) " "Info: Total cell delay = 1.516 ns ( 57.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.130 ns ( 42.71 % ) " "Info: Total interconnect delay = 1.130 ns ( 42.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.646 ns" { CLOCK_27 CLOCK_27~clkctrl audio_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.646 ns" { CLOCK_27 CLOCK_27~combout CLOCK_27~clkctrl audio_outL[0] } { 0.000ns 0.000ns 0.113ns 1.017ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.162 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.162 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } { 0.000ns 1.075ns 1.006ns 1.736ns 1.021ns } { 0.000ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.646 ns" { CLOCK_27 CLOCK_27~clkctrl audio_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.646 ns" { CLOCK_27 CLOCK_27~combout CLOCK_27~clkctrl audio_outL[0] } { 0.000ns 0.000ns 0.113ns 1.017ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 517 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "AUDIO_DAC_ADC.v" "" { Text "C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v" 158 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.162 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.162 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } { 0.000ns 1.075ns 1.006ns 1.736ns 1.021ns } { 0.000ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.646 ns" { CLOCK_27 CLOCK_27~clkctrl audio_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.646 ns" { CLOCK_27 CLOCK_27~combout CLOCK_27~clkctrl audio_outL[0] } { 0.000ns 0.000ns 0.113ns 1.017ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.609 ns - Longest register register " "Info: - Longest register to register delay is 1.609 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns audio_outL\[0\] 1 REG LCFF_X40_Y17_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y17_N1; Fanout = 1; REG Node = 'audio_outL\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { audio_outL[0] } "NODE_NAME" } } { "Noise60hz.v" "" { Text "C:/DE2/NoiseCancel/Noise60hz.v" 517 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.366 ns) 1.609 ns AUDIO_DAC_ADC:u4\|AUD_outL\[0\] 2 REG LCFF_X38_Y15_N1 1 " "Info: 2: + IC(1.243 ns) + CELL(0.366 ns) = 1.609 ns; Loc. = LCFF_X38_Y15_N1; Fanout = 1; REG Node = 'AUDIO_DAC_ADC:u4\|AUD_outL\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.609 ns" { audio_outL[0] AUDIO_DAC_ADC:u4|AUD_outL[0] } "NODE_NAME" } } { "AUDIO_DAC_ADC.v" "" { Text "C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v" 158 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 22.75 % ) " "Info: Total cell delay = 0.366 ns ( 22.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.243 ns ( 77.25 % ) " "Info: Total interconnect delay = 1.243 ns ( 77.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.609 ns" { audio_outL[0] AUDIO_DAC_ADC:u4|AUD_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.609 ns" { audio_outL[0] AUDIO_DAC_ADC:u4|AUD_outL[0] } { 0.000ns 1.243ns } { 0.000ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.162 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.162 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC_ADC:u4|LRCK_1X AUDIO_DAC_ADC:u4|LRCK_1X~clkctrl AUDIO_DAC_ADC:u4|AUD_outL[0] } { 0.000ns 1.075ns 1.006ns 1.736ns 1.021ns } { 0.000ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.646 ns" { CLOCK_27 CLOCK_27~clkctrl audio_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.646 ns" { CLOCK_27 CLOCK_27~combout CLOCK_27~clkctrl audio_outL[0] } { 0.000ns 0.000ns 0.113ns 1.017ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.609 ns" { audio_outL[0] AUDIO_DAC_ADC:u4|AUD_outL[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.609 ns" { audio_outL[0] AUDIO_DAC_ADC:u4|AUD_outL[0] } { 0.000ns 1.243ns } { 0.000ns 0.366ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 " "Info: No valid register-to-register data paths exist for clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}