noise60hz.v

噪生消除的VRILOG实现

output			ENET_CS_N;				//	DM9000A Chip Select
output			ENET_WR_N;				//	DM9000A Write
output			ENET_RD_N;				//	DM9000A Read
output			ENET_RST_N;				//	DM9000A Reset
input			ENET_INT;				//	DM9000A Interrupt
output			ENET_CLK;				//	DM9000A Clock 25 MHz
////////////////////	Audio CODEC		////////////////////////////
output			AUD_ADCLRCK;			//	Audio CODEC ADC LR Clock
input			AUD_ADCDAT;				//	Audio CODEC ADC Data
output			AUD_DACLRCK;			//	Audio CODEC DAC LR Clock
output			AUD_DACDAT;				//	Audio CODEC DAC Data
output			AUD_BCLK;				//	Audio CODEC Bit-Stream Clock
output			AUD_XCK;				//	Audio CODEC Chip Clock
////////////////////	TV Devoder		////////////////////////////
input	[7:0]	TD_DATA;    			//	TV Decoder Data bus 8 bits
input			TD_HS;					//	TV Decoder H_SYNC
input			TD_VS;					//	TV Decoder V_SYNC
output			TD_RESET;				//	TV Decoder Reset
////////////////////////	GPIO	////////////////////////////////
inout	[35:0]	GPIO_0;					//	GPIO Connection 0
inout	[35:0]	GPIO_1;					//	GPIO Connection 1

//	LCD ON
assign	LCD_ON		=	1'b0;
assign	LCD_BLON	=	1'b0;

//	All inout port turn to tri-state
assign	DRAM_DQ		=	16'hzzzz;
assign	FL_DQ		=	8'hzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	OTG_DATA	=	16'hzzzz;
assign	SD_DAT		=	1'bz;
assign	ENET_DATA	=	16'hzzzz;
assign	GPIO_0		=	36'hzzzzzzzzz;
assign	GPIO_1		=	36'hzzzzzzzzz;

wire	VGA_CTRL_CLK;
wire	AUD_CTRL_CLK;
wire	DLY_RST;

assign	TD_RESET	=	1'b1;	//	Allow 27 MHz
assign	AUD_ADCLRCK	=	AUD_DACLRCK;
assign	AUD_XCK		=	AUD_CTRL_CLK;

Reset_Delay			r0	(	.iCLK(CLOCK_50),.oRESET(DLY_RST)	);

VGA_Audio_PLL 		p1	(	.areset(~DLY_RST),.inclk0(CLOCK_27),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(VGA_CLK)	);

I2C_AV_Config 		u3	(	//	Host Side
							.iCLK(CLOCK_50),
							.iRST_N(KEY[0]),
							//	I2C Side
							.I2C_SCLK(I2C_SCLK),
							.I2C_SDAT(I2C_SDAT)	);

AUDIO_DAC_ADC 			u4	(	//	Audio Side
							.oAUD_BCK(AUD_BCLK),
							.oAUD_DATA(AUD_DACDAT),
							.oAUD_LRCK(AUD_DACLRCK),
							.oAUD_inL(audio_inL), // audio data from ADC 
							.oAUD_inR(audio_inR), // audio data from ADC 
							.iAUD_ADCDAT(AUD_ADCDAT),
							.iAUD_extL(audio_outL), // audio data to DAC
							.iAUD_extR(audio_outR), // audio data to DAC
							//	Control Signals
							//.iSrc_Select(SW[17]),
				            .iCLK_18_4(AUD_CTRL_CLK),
							.iRST_N(DLY_RST)
							);

/// reset //////////////////////////////////////						
//state machine start up	
wire reset; 
// reset control
assign reset = ~KEY[0];
///////////////////////////////////////////////

// state variable 
reg [3:0] state ;
//oneshot gen to sync to audio clock
reg last_clk ; 

// output to audio DAC
reg signed [15:0] audio_outL, audio_outR ;

// input from audio ADC
wire signed [15:0] audio_inL, audio_inR;
		

/// memory for phase shifter /////////////////////////////////////////
//memory control
reg we; //write enable--active high
wire [15:0] read_data; 
reg [15:0]  write_data;
reg [7:0] addr_reg;
//pointers into the shift register
//200 samples at 48kHz for 1/4 cycle 60 Hz noise
reg [7:0] ptr_in, ptr_out; 
//make the phase shift register
ram_infer PhaseShifter(read_data, addr_reg, write_data, we, CLOCK_50);	
//////////////////////////////////////////////////////////////////////


/// LMS /////////////////////////////////////////////////////////////
// LMS registers
// 2 weights
reg signed [17:0] w1, w2;
// 2 inputs
reg signed [17:0] ref60, shifted_ref60 ;
// error output (main output)
wire signed [17:0] error_out ;
// two product terms
wire signed [17:0] w1_x_ref, w2_x_shifted_ref;
// mult for weight times ref and weight times phase-shifted ref
signed_mult w1xRef(w1_x_ref, w1, ref60);
signed_mult w2xRefShifted(w2_x_shifted_ref, w2, shifted_ref60) ;
//assume noisy signal is on right channel, ref on left channel
assign error_out = {audio_inR, 2'h0} - (w1_x_ref + w2_x_shifted_ref);
//////////////////////////////////////////////////////////////////////

/*
// loopback test
always @ (posedge AUD_DACLRCK)
begin
	audio_outL <= audio_inL;
	audio_outR <= audio_inR;
end
*/

//debug readouts
assign LEDG[3:0] = state;
assign LEDR[7:0] = ptr_out;

//Run the state machine FAST so that it completes in one 
//audio cycle
always @ (posedge CLOCK_27)
begin
	if (reset)
	begin
		ptr_out <= 8'h1 ; // beginning of shift register
		ptr_in <= 8'h0 ;
		we <= 1'h0 ; 
		state <= 4'd8 ; //turn off the state machine	
		//last_clk <= 1'h1;
	end
	
	else begin
		case (state)
	
			1: 
			begin
				// set up read ptr_out data
				addr_reg <= ptr_out;
				we <= 1'h0;
				
				// next state
				state <= 4'd2;
			end
	
			2: 
			begin
				//get ptr_out data
				shifted_ref60 <= {read_data, 2'h0} ;
					
				// set up write ptr_in data
				addr_reg <= ptr_in;
				we <= 1'h1;
				write_data <= audio_inL ;
				
				// store current ref channel
				ref60 <= {audio_inL, 2'h0} ;
				
				// make some output
				// original signal in R channel
				// denoised signal in L channel
				// audio seems to negate signal, so invert it
				audio_outR <= -audio_inR ;
				audio_outL <= -error_out[17:2];
				
				// next state
				state <= 4'd3;
			end
			
			3:
			begin
				// turn off memroy write
				we <= 1'h0;
				// update weights
				w1 <= w1 + (((ref60[17])? -error_out : error_out)>>>10) ;
				w2 <= w2 + (((shifted_ref60[17])? -error_out : error_out)>>>10) ;
				// next state
				state <= 4'd5;
			end
			
			
			5: 
			begin
				// phase shifter pointer control
				// update write pointer
				if (ptr_in == 8'd200) //200
					ptr_in <= 8'h0;
				else
					ptr_in <= ptr_in + 8'h1 ;
					
				// update read pointer
				if (ptr_out == 8'd200)
					ptr_out <= 8'h0;
				else
					ptr_out <= ptr_out + 8'h1 ;
				
				//next state is end state
				state <= 4'd8;
			end
			
			8:
			begin
				// wait for the audio clock and one-shot it
				if (AUD_DACLRCK && last_clk==1)
				begin
					state <= 4'd1 ;
					last_clk <= 1'h0 ;
				end
				// reset the one-shot memory
				else if (~AUD_DACLRCK && last_clk==0)
				begin
					last_clk <= 1'h1 ;
				end	
			end
			
			default:
			begin
				// default state is end state
				state <= 4'd8 ;
			end
		endcase
	end
end	

endmodule

//////////////////////////////////////////////////
//// M4k ram for circular buffer /////////////////
//////////////////////////////////////////////////
// Synchronous RAM 
// modified for 16 bit access
// of 200 words to tune for 1/4 cycle at 60 Hz
module ram_infer (q, a, d, we, clk);
output reg  [15:0] q;
input [15:0] d;
input [7:0] a;
input we, clk;
 
reg [15:0] mem [255:0];
	always @ (posedge clk) 
	begin
		if (we) mem[a] <= d;
		q <= mem[a] ;
	end
endmodule 
//////////////////////////////////////////////////



//////////////////////////////////////////////////
//// signed mult of 2.16 format 2'comp////////////
//////////////////////////////////////////////////
module signed_mult (out, a, b);

	output 		[17:0]	out;
	input 	signed	[17:0] 	a;
	input 	signed	[17:0] 	b;
	
	wire	signed	[17:0]	out;
	wire 	signed	[35:0]	mult_out;

	assign mult_out = a * b;
	//assign out = mult_out[33:17];
	assign out = {mult_out[35], mult_out[32:16]};
endmodule
//////////////////////////////////////////////////