de2_default.map.rpt

噪生消除的VRILOG实现

+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; DE2_Default        ; DE2_Default        ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                     ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                           ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------------+
; Noise60hz.v                      ; yes             ; User Verilog HDL File        ; C:/DE2/NoiseCancel/Noise60hz.v                                         ;
; I2C_AV_Config.v                  ; yes             ; User Verilog HDL File        ; C:/DE2/NoiseCancel/I2C_AV_Config.v                                     ;
; I2C_Controller.v                 ; yes             ; User Verilog HDL File        ; C:/DE2/NoiseCancel/I2C_Controller.v                                    ;
; Reset_Delay.v                    ; yes             ; User Verilog HDL File        ; C:/DE2/NoiseCancel/Reset_Delay.v                                       ;
; VGA_Audio_PLL.v                  ; yes             ; User Verilog HDL File        ; C:/DE2/NoiseCancel/VGA_Audio_PLL.v                                     ;
; AUDIO_DAC_ADC.v                  ; yes             ; User Verilog HDL File        ; C:/DE2/NoiseCancel/AUDIO_DAC_ADC.v                                     ;
; altpll.tdf                       ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf                 ;
; aglobal60.inc                    ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc              ;
; stratix_pll.inc                  ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc            ;
; stratixii_pll.inc                ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc          ;
; cycloneii_pll.inc                ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc          ;
; sld_signaltap.vhd                ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd          ;
; sld_ela_control.vhd              ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_ela_control.vhd        ;
; lpm_shiftreg.tdf                 ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf           ;
; lpm_constant.inc                 ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/lpm_constant.inc           ;
; dffeea.inc                       ; yes             ; Other                        ; c:/altera/quartus60/libraries/megafunctions/dffeea.inc                 ;
; sld_mbpmg.vhd                    ; yes             ; Encrypted Megafunction       ; c:/altera/quartus60/libraries/megafunctions/sld_mbpmg.vhd              ;
; lpm_counter.tdf                  ; yes             ; Megafunction                 ; c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf            ;