de2_default.map.rpt

噪生消除的VRILOG实现

Analysis & Synthesis report for DE2_Default
Mon Oct 01 08:36:38 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. State Machine - |DE2_Default|state
 10. State Machine - |DE2_Default|I2C_AV_Config:u3|mSetup_ST
 11. General Register Statistics
 12. Inverted Register Statistics
 13. Multiplexer Restructuring Statistics (Restructuring Performed)
 14. Source assignments for sld_signaltap:auto_signaltap_0
 15. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5oi2:auto_generated
 16. Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr
 17. Source assignments for sld_hub:sld_hub_inst
 18. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 19. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 20. Source assignments for ram_infer:PhaseShifter|altsyncram:mem_rtl_0|altsyncram_rsi1:auto_generated
 21. Parameter Settings for User Entity Instance: VGA_Audio_PLL:p1|altpll:altpll_component
 22. Parameter Settings for User Entity Instance: I2C_AV_Config:u3
 23. Parameter Settings for User Entity Instance: AUDIO_DAC_ADC:u4
 24. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 25. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 26. Parameter Settings for Inferred Entity Instance: ram_infer:PhaseShifter|altsyncram:mem_rtl_0
 27. Parameter Settings for Inferred Entity Instance: signed_mult:w2xRefShifted|lpm_mult:Mult0
 28. Parameter Settings for Inferred Entity Instance: signed_mult:w1xRef|lpm_mult:Mult0
 29. lpm_mult Parameter Settings by Entity Instance
 30. SignalTap II Logic Analyzer Settings
 31. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Mon Oct 01 08:36:37 2007        ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition ;
; Revision Name                      ; DE2_Default                                  ;
; Top-level Entity Name              ; DE2_Default                                  ;
; Family                             ; Cyclone II                                   ;
; Total logic elements               ; 607                                          ;
; Total registers                    ; 491                                          ;
; Total pins                         ; 429                                          ;
; Total virtual pins                 ; 0                                            ;
; Total memory bits                  ; 4,608                                        ;
; Embedded Multiplier 9-bit elements ; 4                                            ;
; Total PLLs                         ; 1                                            ;
+------------------------------------+----------------------------------------------+


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; Analysis & Synthesis Settings                                                                                ;