de2_default.tan.rpt

噪生消除的VRILOG实现

; Type                                                          ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                                                                    ; To                                                                                                                                                                                                                      ; From Clock                                     ; To Clock                                       ; Failed Paths ;
+---------------------------------------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+--------------+
; Worst-case tsu                                                ; N/A      ; None                             ; 6.650 ns                         ; KEY[0]                                                                                                                                                                                                                  ; w2[17]                                                                                                                                                                                                                  ; --                                             ; CLOCK_27                                       ; 0            ;
; Worst-case tco                                                ; N/A      ; None                             ; 14.609 ns                        ; I2C_AV_Config:u3|I2C_Controller:u0|SD_COUNTER[2]                                                                                                                                                                        ; I2C_SCLK                                                                                                                                                                                                                ; CLOCK_50                                       ; --                                             ; 0            ;
; Worst-case tpd                                                ; N/A      ; None                             ; 2.612 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                                ; altera_reserved_tdo                                                                                                                                                                                                     ; --                                             ; --                                             ; 0            ;
; Worst-case th                                                 ; N/A      ; None                             ; 1.740 ns                         ; altera_internal_jtag                                                                                                                                                                                                    ; sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8]                                                                                                                                                                                ; --                                             ; altera_internal_jtag~TCKUTAP                   ; 0            ;
; Clock Setup: 'CLOCK_27'                                       ; 0.500 ns ; 27.00 MHz ( period = 37.037 ns ) ; N/A                              ; AUDIO_DAC_ADC:u4|LRCK_1X                                                                                                                                                                                                ; state.0001                                                                                                                                                                                                              ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; CLOCK_27                                       ; 0            ;
; Clock Setup: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk1' ; 8.568 ns ; 18.00 MHz ( period = 55.555 ns ) ; N/A                              ; audio_outL[0]                                                                                                                                                                                                           ; AUDIO_DAC_ADC:u4|AUD_outL[0]                                                                                                                                                                                            ; CLOCK_27                                       ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                   ; N/A      ; None                             ; 143.18 MHz ( period = 6.984 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]                                                                                                                                                                      ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                                                                            ; altera_internal_jtag~TCKUTAP                   ; altera_internal_jtag~TCKUTAP                   ; 0            ;
; Clock Setup: 'CLOCK_50'                                       ; N/A      ; None                             ; 167.11 MHz ( period = 5.984 ns ) ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[3] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_lqf:auto_generated|safe_q[1] ; CLOCK_50                                       ; CLOCK_50                                       ; 0            ;
; Clock Hold: 'VGA_Audio_PLL:p1|altpll:altpll_component|_clk1'  ; 0.391 ns ; 18.00 MHz ( period = 55.555 ns ) ; N/A                              ; AUDIO_DAC_ADC:u4|AUD_inR[6]                                                                                                                                                                                             ; AUDIO_DAC_ADC:u4|AUD_inR[6]                                                                                                                                                                                             ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ; 0            ;
; Clock Hold: 'CLOCK_27'                                        ; 0.391 ns ; 27.00 MHz ( period = 37.037 ns ) ; N/A                              ; we                                                                                                                                                                                                                      ; we                                                                                                                                                                                                                      ; CLOCK_27                                       ; CLOCK_27                                       ; 0            ;
; Total number of failed paths                                  ;          ;                                  ;                                  ;                                                                                                                                                                                                                         ;                                                                                                                                                                                                                         ;                                                ;                                                ; 0            ;
+---------------------------------------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------+------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                  ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+
; Clock Node Name                                ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset     ; Phase offset ;
+------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+------------+--------------+
; VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 18.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 2                     ; 3                   ; -2.384 ns  ;              ;