de2_default.map.summary

来自「噪生消除的VRILOG实现」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Mon Oct 01 08:36:37 2007
Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
Revision Name : DE2_Default
Top-level Entity Name : DE2_Default
Family : Cyclone II
Total logic elements : 607
Total registers : 491
Total pins : 429
Total virtual pins : 0
Total memory bits : 4,608
Embedded Multiplier 9-bit elements : 4
Total PLLs : 1