de2_default.fit.rpt

噪生消除的VRILOG实现

Fitter report for DE2_Default
Mon Oct 01 08:37:14 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Netlist Optimizations
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. Bidir Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. PLL Summary
 13. PLL Usage
 14. Output Pin Default Load For Reported TCO
 15. Fitter Resource Utilization by Entity
 16. Delay Chain Summary
 17. Pad To Core Delay Chain Fanout
 18. Control Signals
 19. Global & Other Fast Signals
 20. Non-Global High Fan-Out Signals
 21. Fitter RAM Summary
 22. Fitter DSP Block Usage Summary
 23. DSP Block Details
 24. Interconnect Usage Summary
 25. LAB Logic Elements
 26. LAB-wide Signals
 27. LAB Signals Sourced
 28. LAB Signals Sourced Out
 29. LAB Distinct Inputs
 30. Fitter Device Options
 31. Advanced Data - General
 32. Advanced Data - Placement Preparation
 33. Advanced Data - Placement
 34. Advanced Data - Routing
 35. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Fitter Summary                                                                    ;
+------------------------------------+----------------------------------------------+
; Fitter Status                      ; Successful - Mon Oct 01 08:37:13 2007        ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition ;
; Revision Name                      ; DE2_Default                                  ;
; Top-level Entity Name              ; DE2_Default                                  ;
; Family                             ; Cyclone II                                   ;
; Device                             ; EP2C35F672C6                                 ;
; Timing Models                      ; Final                                        ;
; Total logic elements               ; 692 / 33,216 ( 2 % )                         ;
; Total registers                    ; 476                                          ;