de2_default.map.talkback.xml

噪生消除的VRILOG实现

		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- Cyclone II</option>
		<setting>Balanced</setting>
		<default_value>Balanced</default_value>
	</row>
	<row>
		<option>Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</option>
		<setting>70</setting>
		<default_value>70</default_value>
	</row>
	<row>
		<option>Auto Carry Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform WYSIWYG Primitive Resynthesis</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform gate-level register retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto ROM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto RAM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Shift Register Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Clock Enable Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Allow Synchronous Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Force Use of Synchronous Clear Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any RAM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any ROM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any Shift Register Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Maximum Number of M4K Memory Blocks</option>
		<setting>Unlimited</setting>
		<default_value>Unlimited</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore Maximum Fan-Out Assignments</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Retiming Meta-Stability Register Sequence Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>HDL message level</option>
		<setting>Level2</setting>
		<default_value>Level2</default_value>
	</row>
</analysis___synthesis_settings>
<general_register_statistics>
	<row>
		<statistic>Total registers</statistic>
		<value>491</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Clear</statistic>
		<value>48</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Load</statistic>
		<value>14</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Clear</statistic>
		<value>193</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Clock Enable</statistic>
		<value>290</value>
	</row>
	<row>
		<statistic>Number of registers using Preset</statistic>
		<value>0</value>
	</row>
</general_register_statistics>
<signaltap_ii_logic_analyzer_settings>
	<row>
		<instance_index>0</instance_index>
		<instance_name>auto_signaltap_0</instance_name>
		<trigger_input_width>4</trigger_input_width>
		<data_input_width>4</data_input_width>
		<sample_depth>128</sample_depth>
		<trigger_levels>1</trigger_levels>
		<advanced_trigger_levels>0</advanced_trigger_levels>
		<trigger_in_used>no</trigger_in_used>
		<trigger_out_used>no</trigger_out_used>
		<power_up_trigger_enabled>no</power_up_trigger_enabled>
		<incremental_trigger_inputs>0</incremental_trigger_inputs>
		<incremental_data_inputs>0</incremental_data_inputs>
	</row>
</signaltap_ii_logic_analyzer_settings>
<ip_cores>
	<ip type="ampp">
			<corename>sld_signaltap.vhd</corename>
		<vendor_id>6AF7</vendor_id>
		<product_id>BCEC</product_id>
		<pof>on</pof>
		<to>on</to>
		<edo_vho_vo>on</edo_vho_vo>
		<source_view>off</source_view>
	</ip>
	<ip type="ampp">
			<corename>sld_ela_control.vhd</corename>
		<vendor_id>6AF7</vendor_id>
		<product_id>BCEC</product_id>
		<pof>on</pof>
		<to>on</to>
		<edo_vho_vo>on</edo_vho_vo>
		<source_view>off</source_view>
	</ip>
	<ip type="ampp">
			<corename>sld_mbpmg.vhd</corename>
		<vendor_id>6AF7</vendor_id>
		<product_id>BCEC</product_id>
		<pof>on</pof>
		<to>on</to>
		<edo_vho_vo>on</edo_vho_vo>
		<source_view>off</source_view>
	</ip>
	<ip type="ampp">
			<corename>sld_acquisition_buffer.vhd</corename>
		<vendor_id>6AF7</vendor_id>
		<product_id>BCEC</product_id>
		<pof>on</pof>
		<to>on</to>
		<edo_vho_vo>on</edo_vho_vo>
		<source_view>off</source_view>
	</ip>
	<ip type="ampp">
			<corename>sld_rom_sr.vhd</corename>
		<vendor_id>6AF7</vendor_id>
		<product_id>BCE1</product_id>
		<pof>on</pof>
		<to>on</to>
		<edo_vho_vo>on</edo_vho_vo>
		<source_view>off</source_view>
	</ip>
	<ip type="ampp">
			<corename>sld_hub.vhd</corename>
		<vendor_id>6AF7</vendor_id>
		<product_id>BCE1</product_id>
		<pof>on</pof>
		<to>on</to>
		<edo_vho_vo>on</edo_vho_vo>
		<source_view>off</source_view>
	</ip>
	<ip type="ampp">
			<corename>sld_dffex.vhd</corename>
		<vendor_id>6AF7</vendor_id>
		<product_id>BCE1</product_id>
		<pof>on</pof>
		<to>on</to>
		<edo_vho_vo>on</edo_vho_vo>
		<source_view>off</source_view>
	</ip>
</ip_cores>
</talkback>