de2_default.fit.talkback.xml

噪生消除的VRILOG实现

		<number_used>0</number_used>
	</row>
	<row>
		<statistic>Dedicated Input Shift Register Chains</statistic>
		<number_used>0</number_used>
	</row>
</dsp_block_usage_summary>
<interconnect_usage_summary>
	<rsc name="Local interconnects" util="1" max=" 33216 " type="int">406 </rsc>
	<rsc name="Block interconnects" util="1" max=" 94460 " type="int">811 </rsc>
	<rsc name="R4 interconnects" util="1" max=" 81294 " type="int">515 </rsc>
	<rsc name="R24 interconnects" util="1" max=" 3091 " type="int">34 </rsc>
	<rsc name="C4 interconnects" util="1" max=" 60840 " type="int">382 </rsc>
	<rsc name="C16 interconnects" util="1" max=" 3315 " type="int">20 </rsc>
	<rsc name="Global clocks" util="100" max=" 16 " type="int">16 </rsc>
	<rsc name="Direct links" util="1" max=" 94460 " type="int">190 </rsc>
</interconnect_usage_summary>
<mep_data>
	<command_line>quartus_fit --read_settings_files=off --write_settings_files=off DE2_Default -c DE2_Default</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Following 357 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results</warning>
	<warning>Warning: Following 155 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results</warning>
	<warning>Warning: Found 377 output pins without output pin load capacitance assignment</warning>
	<warning>Warning: PLL &quot;VGA_Audio_PLL:p1|altpll:altpll_component|pll&quot; output port clk[2] feeds output pin &quot;VGA_CLK&quot; via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance</warning>
	<warning>Warning: PLL &quot;VGA_Audio_PLL:p1|altpll:altpll_component|pll&quot; output port clk[1] feeds output pin &quot;AUD_XCK&quot; via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance</warning>
	<info>Info: Quartus II Fitter was successful. 0 errors, 6 warnings</info>
	<info>Info: Elapsed time: 00:00:27</info>
	<info>Info: Processing ended: Mon Oct 01 08:37:13 2007</info>
	<info>Info: Following groups of pins have the same output enable</info>
	<info>Info: Following pins have the same output enable: I2C_AV_Config:u3|I2C_Controller:u0|SDO</info>
</messages>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>EP2C35F672C6</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Router Timing Optimization Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Hold Timing</option>
		<setting>IO Paths and Minimum TPD Paths</setting>
		<default_value>IO Paths and Minimum TPD Paths</default_value>
	</row>
	<row>
		<option>Optimize Fast-Corner Timing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Aggressive Routability Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>PCI I/O</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Weak Pull-Up Resistor</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Enable Bus-Hold Circuitry</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Memory Control Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Packed Registers -- Stratix II/Cyclone II</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Delay Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Merge PLLs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore PLL Mode When Merging PLLs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Physical Synthesis Effort Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Always Enable Input Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Active Serial</setting>
	</row>
	<row>
		<option>Error detection CRC</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Reserve ASDO pin after configuration.</option>
		<setting>As input tri-stated</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As input tri-stated</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>AUD_ADCDAT</name>
		<pin__>B5</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>3</x_coordinate>
		<y_coordinate>36</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>32</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>CLOCK_27</name>
		<pin__>D13</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>31</x_coordinate>
		<y_coordinate>36</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>2</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>CLOCK_50</name>
		<pin__>N2</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>0</x_coordinate>
		<y_coordinate>18</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>ENET_INT</name>
		<pin__>B21</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>59</x_coordinate>
		<y_coordinate>36</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>0</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>EXT_CLOCK</name>
		<pin__>P26</pin__>
		<i_o_bank>6</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>19</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>0</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>IRDA_RXD</name>
		<pin__>AE25</pin__>
		<i_o_bank>6</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>2</y_coordinate>
		<cell_number>3</cell_number>
		<combinational_fan_out>0</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>KEY[0]</name>
		<pin__>G26</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>27</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>59</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>KEY[1]</name>
		<pin__>N23</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>20</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>KEY[2]</name>
		<pin__>P23</pin__>
		<i_o_bank>6</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>18</y_coordinate>
		<cell_number>0</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>KEY[3]</name>
		<pin__>W26</pin__>
		<i_o_bank>6</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>10</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>1</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>