de2_default.fit.talkback.xml

噪生消除的VRILOG实现

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from the compilation of logic designs using Quartus II software (BUT NOT THE
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<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_202.xsd</schema>
<license>
	<host_id>00123f4b0b3f</host_id>
	<nic_id>00123f4b0b3f</nic_id>
	<cdrive_id>882dfa9e</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 202</build>
	<service_pack_label>1</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_fit</module>
	<edition>Web Edition</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Mon Oct 01 08:37:14 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">3391</cpu_freq>
	</cpu>
	<ram units="MB">1023</ram>
</machine>
<project>C:/DE2/NoiseCancel/DE2_Default</project>
<revision>DE2_Default</revision>
<compilation_summary>
	<flow_status>Successful - Mon Oct 01 08:37:13 2007</flow_status>
	<quartus_ii_version>6.0 Build 202 06/20/2006 SP 1 SJ Web Edition</quartus_ii_version>
	<revision_name>DE2_Default</revision_name>
	<top_level_entity_name>DE2_Default</top_level_entity_name>
	<family>Cyclone II</family>
	<device>EP2C35F672C6</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>692 / 33,216 ( 2 % )</total_logic_elements>
	<total_registers>476</total_registers>
	<total_pins>429 / 475 ( 90 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>4,608 / 483,840 ( &lt; 1 % )</total_memory_bits>
	<embedded_multiplier_9_bit_elements>4 / 70 ( 6 % )</embedded_multiplier_9_bit_elements>
	<total_plls>1 / 4 ( 25 % )</total_plls>
</compilation_summary>
<resource_usage_summary>
	<rsc name="Total logic elements" util="2" max=" 33216 " type="int">692 </rsc>
	<rsc name="-- Combinational with no register" type="int">216</rsc>
	<rsc name="-- Register only" type="int">84</rsc>
	<rsc name="-- Combinational with a register" type="int">392</rsc>
	<rsc name="Logic element usage by number of LUT inputs" type="text"></rsc>
	<rsc name="-- 4 input functions" type="int">236</rsc>
	<rsc name="-- 3 input functions" type="int">165</rsc>
	<rsc name="-- &lt;=2 input functions" type="int">207</rsc>
	<rsc name="-- Register only" type="int">84</rsc>
	<rsc name="Logic elements by mode" type="text"></rsc>
	<rsc name="-- normal mode" type="int">401</rsc>
	<rsc name="-- arithmetic mode" type="int">207</rsc>
	<rsc name="Total registers" util="1" max=" 33216 " type="int">476 </rsc>
	<rsc name="Total LABs" util="3" max=" 2076 " type="int">61 </rsc>
	<rsc name="User inserted logic elements" type="int">0</rsc>
	<rsc name="Virtual pins" type="int">0</rsc>
	<rsc name="I/O pins" util="90" max=" 475 " type="int">429 </rsc>
	<rsc name="-- Clock pins" util="100" max=" 8 " type="int">8 </rsc>
	<rsc name="Global signals" type="int">16</rsc>
	<rsc name="M4Ks" util="2" max=" 105 " type="int">2 </rsc>
	<rsc name="Total memory bits" util="1" max=" 483840 " type="int">4608 </rsc>
	<rsc name="Total RAM block bits" util="2" max=" 483840 " type="int">9216 </rsc>
	<rsc name="Embedded Multiplier 9-bit elements" util="6" max=" 70 " type="int">4 </rsc>
	<rsc name="PLLs" util="25" max=" 4 " type="int">1 </rsc>
	<rsc name="Global clocks" util="100" max=" 16 " type="int">16 </rsc>
	<rsc name="Maximum fan-out node" type="text">altera_internal_jtag~TCKUTAPclkctrl</rsc>
	<rsc name="Maximum fan-out" type="int">139</rsc>
	<rsc name="Highest non-global fan-out signal" type="text">KEY[0]</rsc>
	<rsc name="Highest non-global fan-out" type="int">59</rsc>
	<rsc name="Total fan-out" type="int">3523</rsc>
	<rsc name="Average fan-out" type="float">2.21</rsc>
</resource_usage_summary>
<pll_summary>
	<row>
		<name>VGA_Audio_PLL:p1|altpll:altpll_component|pll</name>
		<pll_mode>Normal</pll_mode>
		<compensate_clock>clock1</compensate_clock>
		<input_frequency_0 units="MHz">27.0</input_frequency_0>
		<nominal_vco_frequency units="MHz">377.9</nominal_vco_frequency>
		<freq_min_lock units="MHz">21.43</freq_min_lock>
		<freq_max_lock units="MHz">35.71</freq_max_lock>
		<m_vco_tap>6</m_vco_tap>
		<m_initial>4</m_initial>
		<m_value>14</m_value>
		<n_value>1</n_value>
		<pll_location>PLL_3</pll_location>
		<pll_inclk0_signal>CLOCK_27</pll_inclk0_signal>
		<pll_inclk0_signal_type>Dedicated Pin</pll_inclk0_signal_type>
	</row>
</pll_summary>
<pll_usage>
	<row>
		<name>VGA_Audio_PLL:p1|altpll:altpll_component|_clk1</name>
		<output_clock>clock1</output_clock>
		<mult>2</mult>
		<div>3</div>
		<output_frequency units="MHz">18.0</output_frequency>
		<phase_shift>0 (0 ps)</phase_shift>
		<duty_cycle>50/50</duty_cycle>
		<counter>C0</counter>
		<counter_value>21</counter_value>
		<high___low>11/10 Odd</high___low>
		<initial>4</initial>
		<vco_tap>6</vco_tap>
	</row>
	<row>
		<name>VGA_Audio_PLL:p1|altpll:altpll_component|_clk2</name>
		<output_clock>clock2</output_clock>
		<mult>14</mult>
		<div>15</div>
		<output_frequency units="MHz">25.2</output_frequency>
		<phase_shift>-90 (-9921 ps)</phase_shift>
		<duty_cycle>50/50</duty_cycle>
		<counter>C1</counter>
		<counter_value>15</counter_value>
		<high___low>8/7 Odd</high___low>
		<initial>1</initial>
		<vco_tap>0</vco_tap>
	</row>
</pll_usage>
<control_signals>
	<row>
		<name>CLOCK_27</name>
		<location>PIN_D13</location>
		<fan_out>2</fan_out>
		<usage>Clock</usage>
		<global>no</global>
	</row>
	<row>
		<name>AUDIO_DAC_ADC:u4|oAUD_BCK</name>
		<location>LCFF_X64_Y19_N31</location>
		<fan_out>36</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK5</global_line_name>
	</row>
	<row>
		<name>I2C_AV_Config:u3|mI2C_CTRL_CLK</name>
		<location>LCFF_X54_Y19_N27</location>
		<fan_out>44</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK4</global_line_name>
	</row>
	<row>
		<name>altera_internal_jtag~TCKUTAP</name>
		<location>JTAG_X1_Y19_N0</location>
		<fan_out>139</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK1</global_line_name>
	</row>
	<row>
		<name>CLOCK_50</name>
		<location>PIN_N2</location>
		<fan_out>98</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK2</global_line_name>
	</row>
	<row>
		<name>CLOCK_27</name>
		<location>PIN_D13</location>
		<fan_out>118</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK9</global_line_name>
	</row>
	<row>
		<name>sld_signaltap:auto_signaltap_0|reset_all</name>
		<location>LCCOMB_X45_Y19_N8</location>
		<fan_out>77</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK8</global_line_name>
	</row>
	<row>
		<name>VGA_Audio_PLL:p1|altpll:altpll_component|_clk1</name>
		<location>PLL_3</location>
		<fan_out>15</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK11</global_line_name>
	</row>
	<row>
		<name>Reset_Delay:r0|oRESET</name>
		<location>LCFF_X37_Y12_N9</location>
		<fan_out>19</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK12</global_line_name>
	</row>
	<row>
		<name>AUDIO_DAC_ADC:u4|LRCK_1X</name>
		<location>LCFF_X37_Y15_N17</location>
		<fan_out>32</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK14</global_line_name>
	</row>
	<row>
		<name>sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]</name>
		<location>LCFF_X44_Y19_N17</location>
		<fan_out>13</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK15</global_line_name>
	</row>
	<row>
		<name>sld_hub:sld_hub_inst|CLR_SIGNAL</name>
		<location>LCFF_X45_Y19_N19</location>
		<fan_out>26</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK0</global_line_name>
	</row>
	<row>
		<name>sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|offload_shift_ena</name>
		<location>LCCOMB_X46_Y19_N14</location>
		<fan_out>2</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK3</global_line_name>
	</row>
	<row>
		<name>sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]</name>
		<location>LCFF_X45_Y19_N29</location>
		<fan_out>2</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK7</global_line_name>
	</row>
	<row>
		<name>sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset</name>
		<location>LCCOMB_X46_Y19_N4</location>
		<fan_out>7</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK6</global_line_name>
	</row>
	<row>
		<name>sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|gen_non_zero_sample_depth~0</name>
		<location>LCCOMB_X45_Y19_N6</location>
		<fan_out>7</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK13</global_line_name>
	</row>
</control_signals>
<non_global_high_fan_out_signals>
	<row>
		<name>state.0010</name>
		<fan_out>13</fan_out>
	</row>
	<row>
		<name>state.1000</name>
		<fan_out>6</fan_out>
	</row>
	<row>
		<name>LEDG~1</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>state.0011</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>LEDG~0</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>state.0101</name>
		<fan_out>4</fan_out>
	</row>
	<row>
		<name>ptr_out[0]</name>
		<fan_out>5</fan_out>
	</row>
	<row>
		<name>ptr_out[1]</name>
		<fan_out>4</fan_out>
	</row>
	<row>
		<name>ptr_out[2]</name>
		<fan_out>4</fan_out>
	</row>
	<row>
		<name>ptr_out[3]</name>
		<fan_out>4</fan_out>
	</row>
</non_global_high_fan_out_signals>
<ram_summary>
	<row>
		<name>ram_infer:PhaseShifter|altsyncram:mem_rtl_0|altsyncram_rsi1:auto_generated|ALTSYNCRAM</name>
		<type>AUTO</type>
		<mode>Simple Dual Port</mode>
		<port_a_depth>256</port_a_depth>
		<port_a_width>16</port_a_width>
		<port_b_depth>256</port_b_depth>
		<port_b_width>16</port_b_width>
		<port_a_input_registers>yes</port_a_input_registers>
		<port_a_output_registers>no</port_a_output_registers>
		<port_b_input_registers>yes</port_b_input_registers>
		<port_b_output_registers>no</port_b_output_registers>
		<size>4096</size>
		<m4ks>1</m4ks>
		<mif>None</mif>
		<location>M4K_X52_Y17</location>
	</row>
	<row>
		<name>sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5oi2:auto_generated|ALTSYNCRAM</name>
		<type>AUTO</type>
		<mode>Simple Dual Port</mode>
		<port_a_depth>128</port_a_depth>
		<port_a_width>4</port_a_width>
		<port_b_depth>128</port_b_depth>
		<port_b_width>4</port_b_width>
		<port_a_input_registers>yes</port_a_input_registers>
		<port_a_output_registers>no</port_a_output_registers>
		<port_b_input_registers>yes</port_b_input_registers>
		<port_b_output_registers>no</port_b_output_registers>
		<size>512</size>
		<m4ks>1</m4ks>
		<mif>None</mif>
		<location>M4K_X52_Y20</location>
	</row>
</ram_summary>
<dsp_block_usage_summary>
	<row>
		<statistic>Simple Multipliers (9-bit)</statistic>
		<number_used>0</number_used>
		<available_per_block>2</available_per_block>
		<maximum_available>70</maximum_available>
	</row>
	<row>
		<statistic>Simple Multipliers (18-bit)</statistic>
		<number_used>2</number_used>
		<available_per_block>1</available_per_block>
		<maximum_available>35</maximum_available>
	</row>
	<row>
		<statistic>Embedded Multiplier Blocks</statistic>
		<number_used>2</number_used>
		<maximum_available>35</maximum_available>
	</row>
	<row>
		<statistic>Embedded Multiplier 9-bit elements</statistic>
		<number_used>4</number_used>
		<available_per_block>2</available_per_block>
		<maximum_available>70</maximum_available>
	</row>
	<row>
		<statistic>Signed Embedded Multipliers</statistic>
		<number_used>2</number_used>
	</row>
	<row>
		<statistic>Unsigned Embedded Multipliers</statistic>
		<number_used>0</number_used>
	</row>
	<row>
		<statistic>Mixed Sign Embedded Multipliers</statistic>
		<number_used>0</number_used>
	</row>
	<row>
		<statistic>Variable Sign Embedded Multipliers</statistic>