forwardunit.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

-- forwardunit.vhdl
--
-- forward unit
-- 

library ieee;
use ieee.std_logic_1164.all;
use work.mips_pack.all;


entity fu is 
   port(instr: in std_ulogic_vector(15 downto 0);
        reg_we: in std_ulogic;
        reg_we_d: in std_ulogic;
        rst: in std_ulogic;
	     clk: in std_ulogic;
        wr_addr: in std_ulogic_vector(4 downto 0);
        wr_addr_d: in std_ulogic_vector(4 downto 0);
        mux1_ctl: out std_ulogic_vector(1 downto 0);
        mux2_ctl: out std_ulogic_vector(1 downto 0);
        mux4_ctl: out std_ulogic_vector(1 downto 0));
end entity;

architecture behavior of fu is
    signal mux4_ctl_u: std_ulogic_vector(1 downto 0);
    signal op: std_ulogic_vector(5 downto 0);
    signal rs,rt: std_ulogic_vector(4 downto 0);
    begin
        op <= instr(15 downto 10);
        rs <= instr(9 downto 5);
        rt <= instr(4 downto 0);

        logic:  process(reg_we,reg_we_d,wr_addr,wr_addr_d,op,rs,rt)
            begin
                --default values
                mux1_ctl <="00" ;
                mux2_ctl <="00" ;
                mux4_ctl_u <="00" ;
                
                case op is 
                    when "000000" =>
                        if (reg_we_d = '1') then
                            if (wr_addr_d = rs) then 
                                mux1_ctl <= "10";
                            elsif (wr_addr_d = rt) then 
                                mux2_ctl <= "10";
                            end if ;
                        end if;
                        if (reg_we = '1') then
                            if (wr_addr = rs) then 
                                mux1_ctl <= "01" ;
                            elsif (wr_addr = rt) then 
                                mux2_ctl <= "01";
                            end if ;
                        end if;
                    when BEQ|BNE|BGTZ|BLTZ|SLT =>
                        if (reg_we_d = '1') then
                            if (wr_addr_d = rs) then 
                                mux1_ctl <= "10";
                            elsif (wr_addr_d = rt) then 
                                mux2_ctl <= "10";
                            end if ;
                        end if;
                        if (reg_we = '1') then
                            if (wr_addr = rs) then 
                                mux1_ctl <= "01";
                            elsif (wr_addr = rt) then 
                                mux2_ctl <= "01";
                            end if ;
                        end if;
                    when SW|SB =>
                        if (reg_we_d = '1') then
                            if (wr_addr_d = rs) then 
                                mux1_ctl <= "10";
                            elsif(wr_addr_d = rt) then
                                mux4_ctl_u <= "10";  
                            end if;
                        end if;
                        if (reg_we = '1') then
                            if (wr_addr = rs) then 
                                mux1_ctl <= "01";
                            elsif(wr_addr = rt) then
                                mux4_ctl_u <= "01";  
                            end if;
                        end if;
                    when ADDIU|ADDI|LW|LBU =>
                        if (reg_we = '1') and (wr_addr = rs) then 
                            mux1_ctl <= "01";
                        elsif (reg_we_d = '1') and (wr_addr_d = rs) then 
                            mux1_ctl <= "10";
                        end if;   
                    when others =>
                        null;
                end case;
            end process;
            
       reg: process(rst,clk)
            begin
                if ( rst = '1') then
                    mux4_ctl <="00" ;
                elsif rising_edge(clk) then 
                    mux4_ctl <= mux4_ctl_u ; 
                end if ;
            end process ;
        end architecture;