mux56.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

library ieee;
use ieee.std_logic_1164.all;
use work.mips_pack.all;

entity mux56 is
   port (data0_in: in std_ulogic_vector (31 downto 0);
         data1_in: in std_ulogic_vector (31 downto 0);
         ctl: in std_ulogic;
         data_out: out std_ulogic_vector (31 downto 0)
         );
end entity mux56;


architecture behavior of mux56 is
begin

-- combinational logic for next AUX value
data_out <= data1_in when (ctl = '1') else
data0_in when (ctl = '0') else
(others => '-');

end architecture behavior;