add4.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

--increase pc by 4 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mips_pack.all;


entity pcadd4 is
	port (pc_in: in std_ulogic_vector(31 downto 0);
	      pc_out: out std_ulogic_vector(31 downto 0)
	     );
end entity pcadd4;


architecture a1 of pcadd4 is
	-- Internally we use unsigned values
	signal  pc_in_u: unsigned(31 downto 0);
	
	-- Hint to synthesis tool on how to use adder
	signal adder_out: unsigned(31 downto 0);
begin
	-- Convert to unsigned from std_ulogic_vector
	pc_in_u <= unsigned(pc_in);

	ALU: process ( pc_in_u, adder_out) is
	begin
				adder_out <= pc_in_u + 4;
				pc_out <= std_ulogic_vector(adder_out);

	end process ALU;
end architecture a1;