mux12.vhd

来自「modelsim+dc开发的4级流水线结构的MIPS CPU」· VHDL 代码 · 共 47 行

--mux12
library ieee;
use ieee.std_logic_1164.all;
use work.mips_pack.all;

entity mux12 is
   port (data0_in: in std_ulogic_vector (31 downto 0);
         data1_in: in std_ulogic_vector (31 downto 0);
         fdata1_in: in std_ulogic_vector (31 downto 0);
         fdata2_in: in std_ulogic_vector (31 downto 0);
         cu_ctl: in std_ulogic;
         fu_ctl: in std_ulogic_vector(1 downto 0);
         data_out: out std_ulogic_vector (31 downto 0)
         );
end entity mux12;

architecture behavior of mux12 is
begin

process( fu_ctl,cu_ctl,data0_in,data1_in,fdata1_in,fdata2_in)
    begin
 --combinational logic for next  value
--data_out <= fdata1_in when (fu_ctl = "01") else
--fdata2_in when (fu_ctl = "10") else 
--data0_in when (fu_ctl = "00") and (cu_ctl = '0') else 
--data1_in when (fu_ctl = "00") and (cu_ctl = '1') else
--(others => '-');
case fu_ctl is 
    when "00" =>
        if (cu_ctl = '0') then 
            data_out <= data0_in;
        elsif (cu_ctl ='1') then 
            data_out <= data1_in;
        else
            data_out <= (others => '-');
        end if;
    when "01" =>
        data_out <= fdata1_in;
    when "10" =>
        data_out <= fdata2_in;
    when others =>
        data_out <= (others=> '-');
end case;
end process;

end architecture behavior;