compare.vhd

来自「modelsim+dc开发的4级流水线结构的MIPS CPU」· VHDL 代码 · 共 29 行

--compare the data out of mux1 and mux2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mips_pack.all;


entity compare is
	port (mux1_in: in std_ulogic_vector(31 downto 0);
	      mux2_in: in std_ulogic_vector(31 downto 0);
	      s_out: out std_ulogic;
	      e_out: out std_ulogic
	     );
end entity compare;


architecture cmp of compare is
begin
    process(mux1_in,mux2_in)
        begin
            s_out <= not mux1_in(31); 
            if (mux1_in xor mux2_in) = X"00000000" then
                e_out <= '1';
            else 
                e_out <= '0';
            end if;
    end process;
end architecture;