mips_cpu.vhd.bak

modelsim+dc开发的4级流水线结构的MIPS CPU

-- vpu.vhdl
--
-- the whole cpu
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mips_pack.all;

entity cpu is
    port(rst: in std_ulogic;
			clk: in std_ulogic;
         ins: in std_ulogic_vector(31 downto 0);
         iaddr: out std_ulogic_vector(31 downto 0);
     			ird: out std_ulogic;
         data_in: in std_ulogic_vector(31 downto 0);
         data_out: out std_ulogic_vector(31 downto 0);
         daddr: out std_ulogic_vector(31 downto 0);
         drd: out std_ulogic;
			dwr: out std_ulogic;
			sel: out std_ulogic
			);
end entity;	

architecture mips of cpu is 
component pcadd4 is
	port (pc_in: in std_ulogic_vector(31 downto 0);
	      pc_out: out std_ulogic_vector(31 downto 0)
	     );
end component pcadd4;
component pcalu is
	port (mux3_in: in std_ulogic_vector(31 downto 0);
	      pc_in: in std_ulogic_vector(31 downto 0);
	      pc_ctl: in std_ulogic;
	      pc_out: out std_ulogic_vector(31 downto 0)
	     );
end component pcalu;
component compare is
	port (mux1_in: in std_ulogic_vector(31 downto 0);
	      mux2_in: in std_ulogic_vector(31 downto 0);
	      s_out: out std_ulogic;
	      e_out: out std_ulogic
	     );
end component compare;
component alu is
	port (mux1_in: in std_ulogic_vector(31 downto 0);
	      mux2_in: in std_ulogic_vector(31 downto 0);
	      alu_ctl: in std_ulogic_vector(5 downto 0);
	      alu_shamt: in std_ulogic_vector(4 downto 0);
	      alu_result: out std_ulogic_vector(31 downto 0);
	      of_out: out std_ulogic
	      );
end component alu;
component branch is
    port(zero_in: in std_ulogic;
        sign_in: in std_ulogic;
        op_in:    in std_ulogic_vector(2 downto 0);
        pcsrc:    out std_ulogic;
        pcbrch:   out std_ulogic
        );
end component branch;
component cu is
	port (instr_in: in std_ulogic_vector(31 downto 0);
	      pc_next: in std_ulogic_vector(3 downto 0);
	      branch_in: in std_ulogic;
	      rst: in std_ulogic;
	      clk: in std_ulogic;
	      alu_ctl: out std_ulogic_vector(5 downto 0);
	      alu_shamt: out std_ulogic_vector(4 downto 0);
	      pcalu_ctl: out std_ulogic;
	      branch_ctl: out std_ulogic_vector(2 downto 0);
	      mux1_ctl: out std_ulogic;
	      mux2_ctl: out std_ulogic;
	      mux3_ctl: out std_ulogic_vector(1 downto 0);
	      mux5_ctl_d: out std_ulogic;
	      instr_re: out std_ulogic;                   
	      reg_we: out std_ulogic;
	      reg_we_d: out std_ulogic;
	      reg_we_dd: out std_ulogic;
	      mem_we: out std_ulogic;
	      mem_we_d: out std_ulogic;
	      mem_re: out std_ulogic;
	      mem_re_d: out std_ulogic;
	      mem_word: out std_ulogic;
	      mem_word_d: out std_ulogic;
	      imm_out: out std_ulogic_vector(31 downto 0);
	      target: out std_ulogic_vector(31 downto 0);
	      pc_rel: out std_ulogic_vector(31 downto 0);
	      wr_addr: out std_ulogic_vector(4 downto 0);
	      wr_addr_d: out std_ulogic_vector(4 downto 0);
	      wr_addr_dd: out std_ulogic_vector(4 downto 0)
	     );
end component cu;
component fu is 
   port(instr: in std_ulogic_vector(31 downto 0);
        reg_we: in std_ulogic;
        reg_we_d: in std_ulogic;
        rst: in std_ulogic;
	     clk: in std_ulogic;
        wr_addr: in std_ulogic_vector(4 downto 0);
        wr_addr_d: in std_ulogic_vector(4 downto 0);
        mux1_ctl: out std_ulogic_vector(1 downto 0);
        mux2_ctl: out std_ulogic_vector(1 downto 0);
        mux4_ctl: out std_ulogic_vector(1 downto 0)
        );
end component;
component mux_3 is
   port (data0_in: in std_ulogic_vector (31 downto 0);
         data1_in: in std_ulogic_vector (31 downto 0);
         data2_in: in std_ulogic_vector (31 downto 0);
         cu_ctl: in std_ulogic_vector(1 downto 0);
         data_out: out std_ulogic_vector (31 downto 0)
         );
end component mux_3;
component mux_4 is
   port (data_in: in std_ulogic_vector (31 downto 0);
         fdata1_in: in std_ulogic_vector (31 downto 0);
         fdata2_in: in std_ulogic_vector (31 downto 0);
         fu_ctl: in std_ulogic_vector(1 downto 0);
         data_out: out std_ulogic_vector (31 downto 0)
         );
end component mux_4;
component mux56 is
   port (data0_in: in std_ulogic_vector (31 downto 0);
         data1_in: in std_ulogic_vector (31 downto 0);
         ctl: in std_ulogic;
         data_out: out std_ulogic_vector (31 downto 0)
         );
end component mux56;
component mux12 is
   port (data0_in: in std_ulogic_vector (31 downto 0);
         data1_in: in std_ulogic_vector (31 downto 0);
         fdata1_in: in std_ulogic_vector (31 downto 0);
         fdata2_in: in std_ulogic_vector (31 downto 0);
         cu_ctl: in std_ulogic;
         fu_ctl: in std_ulogic_vector(1 downto 0);
         data_out: out std_ulogic_vector (31 downto 0)
         );
end component mux12;
component regfile is
	port (reg_r1: in std_ulogic_vector(4 downto 0);
	      reg_r2: in std_ulogic_vector(4 downto 0);
	      reg_w: in std_ulogic_vector(4 downto 0);
	      data_in: in std_ulogic_vector(31 downto 0);
	      clk: in std_ulogic;
	      rst: in std_ulogic;
	      we: in std_ulogic;
	      data_out1: out std_ulogic_vector(31 downto 0);
	      data_out2: out std_ulogic_vector(31 downto 0)
	      );
end component regfile;

signal cu_instr_in,cu_imm_out: std_ulogic_vector(31 downto 0);
signal pcsrc,cu_branch_in: std_ulogic;
signal cu_instr_re: std_ulogic;
signal cu_alu_ctl: std_ulogic_vector(5 downto 0);
signal cu_alu_shamt: std_ulogic_vector(4 downto 0);
signal cu_pcalu_ctl: std_ulogic;
signal cu_branch_ctl: std_ulogic_vector(2 downto 0);
signal cu_mux1_ctl: std_ulogic;
signal cu_mux2_ctl: std_ulogic;
signal cu_mux3_ctl: std_ulogic_vector(1 downto 0);
signal cu_mux5_ctl_d: std_ulogic;                  
signal cu_reg_we: std_ulogic;
signal cu_reg_we_d: std_ulogic;
signal cu_reg_we_dd: std_ulogic;
signal cu_mem_we: std_ulogic;
signal cu_mem_we_d: std_ulogic;
signal cu_mem_re: std_ulogic;
signal cu_mem_re_d: std_ulogic;
signal cu_mem_word: std_ulogic;
signal cu_mem_word_d: std_ulogic;
signal cu_wr_addr: std_ulogic_vector(4 downto 0);
signal cu_wr_addr_d: std_ulogic_vector(4 downto 0);
signal cu_wr_addr_dd: std_ulogic_vector(4 downto 0);
signal mux1_out,mux2_out,mux3_out,mux4_out,mux5_out,mux6_out: std_ulogic_vector(31 downto 0);
signal regfile0,regfile1,data_reg0,data_reg1,data_reg2,alu_result,alu_reg_out,data_wr,pc_add_reg_out: std_ulogic_vector(31 downto 0);
signal pc,pc_next,pc_add_out,pc_next_reg0,pc_next_reg1,cu_pc_rel,cu_target: std_ulogic_vector(31 downto 0);
signal fu_mux1_ctl: std_ulogic_vector(1 downto 0);
signal fu_mux2_ctl: std_ulogic_vector(1 downto 0);
signal fu_mux4_ctl: std_ulogic_vector(1 downto 0);
signal equal_out : std_ulogic;
signal sign_out : std_ulogic;
signal of_out: std_ulogic;

begin
    
   drd <= cu_mem_re_d;
   dwr <= cu_mem_we_d;
   daddr <= alu_reg_out;
   iaddr <= pc;
   ird <= cu_instr_re;
   sel <= cu_mem_word_d;
   pc_reg: component reg   
      generic map(RST_DATA => X"80020000")
	   port map (D => mux6_out,
	             Q => pc,
	             rst => rst, 
	             clk => clk, 
	             we => '1'
	             );
	             
	mux6: component mux56 
      port map(data0_in => pc_next,
               data1_in => pc_add_out,
               ctl => pcsrc,
               data_out => mux6_out
               );  
                     
   pc_add4: component pcadd4 
	   port map(pc_in => pc ,
	            pc_out => pc_next
	            );
	            
   pcnext_reg0: component reg   
	   port map(D => pc_next,
	            Q => pc_next_reg0,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );	
	             
	instr_reg: component reg   
	   port map(D => ins,
	            Q => cu_instr_in,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );	
	              
	reg_file:component regfile 
	   port map(reg_r1 => cu_instr_in(25 downto 21),
	            reg_r2 => cu_instr_in(20 downto 16),
	            reg_w => cu_wr_addr_dd,
	            data_in => data_wr,
	            clk => clk,
	            rst => rst,
	            we => cu_reg_we_dd,
	            data_out1 => regfile0,
	            data_out2 => regfile1
	            );
	         
	control:component cu 
	   port map(cu_instr_in,
	            pc_next_reg0(31 downto 28),
	            cu_branch_in,
	            rst,
	            clk,
	            cu_alu_ctl,
	            cu_alu_shamt,
	            cu_pcalu_ctl,
	            cu_branch_ctl,
	            cu_mux1_ctl,
	            cu_mux2_ctl,
	            cu_mux3_ctl,
	            cu_mux5_ctl_d,
	            cu_instr_re,                  
	            cu_reg_we,
	            cu_reg_we_d,
	            cu_reg_we_dd,
	            cu_mem_we,
	            cu_mem_we_d,
	            cu_mem_re,
	            cu_mem_re_d,
	            cu_mem_word,
	            cu_mem_word_d,
	            cu_imm_out,
	            cu_target,
	            cu_pc_rel,
	            cu_wr_addr,
	            cu_wr_addr_d,
	            cu_wr_addr_dd
	            );                      	                        
                
   forward: component fu 
      port map(instr => cu_instr_in(31 downto 16),
              reg_we => cu_reg_we,
              reg_we_d => cu_reg_we_d,
              rst => rst,
	           clk => clk,
              wr_addr => cu_wr_addr,
              wr_addr_d => cu_wr_addr_d,
              mux1_ctl => fu_mux1_ctl,
              mux2_ctl => fu_mux2_ctl,
              mux4_ctl => fu_mux4_ctl
              );	
	  
	mux3: component mux_3 
      port map(data0_in => regfile0,
               data1_in => cu_pc_rel,
               data2_in => cu_target,
               cu_ctl => cu_mux3_ctl,
               data_out => mux3_out
               );
   
   mux1: component mux12 
      port map(data0_in => regfile0,
               data1_in => pc_next_reg0,
               fdata1_in => alu_result,
               fdata2_in => mux5_out,
               cu_ctl => cu_mux1_ctl,
               fu_ctl => fu_mux1_ctl,
               data_out => mux1_out
               );  
               
   mux2: component mux12 
      port map(data0_in => regfile1,
               data1_in => cu_imm_out,
               fdata1_in => alu_result,
               fdata2_in => mux5_out,
               cu_ctl => cu_mux2_ctl,
               fu_ctl => fu_mux2_ctl,
               data_out => mux2_out
               );
               
   cmpr: component compare 
	   port map(mux1_in => data_reg0,
	            mux2_in => data_reg1,
	            s_out => sign_out,
	            e_out => equal_out
	            );
               
   pc_add: component pcalu 
	   port map(mux3_in => data_reg2,
	            pc_in => pc_next_reg1,
	            pc_ctl => cu_pcalu_ctl,
	            pc_out => pc_add_out
	            );
	            
	pcnext_reg1: component reg   
	   port map(D => pc_next_reg0,
	            Q => pc_next_reg1,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );
	                          
   data_register0: component reg   
	   port map(D => mux1_out,
	            Q => data_reg0,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );           
	            
	data_register1: component reg   
	   port map(D => mux2_out,
	            Q => data_reg1,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );
	 data_register2: component reg   
	   port map(D => mux3_out,
	            Q => data_reg2,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );	 
	            
	main_alu: component alu 
	   port map(mux1_in => data_reg0,
	            mux2_in => data_reg1,
	            alu_ctl => cu_alu_ctl,
	            alu_shamt => cu_alu_shamt,
	            alu_result => alu_result,
	            of_out => of_out
	            );
	            
	branch_l: component branch 
      port map(zero_in => equal_out,
               sign_in => sign_out,
               op_in => cu_branch_ctl,
               pcsrc => pcsrc,
               pcbrch => cu_branch_in
               );
               
	mux4: component mux_4 
      port map(data_in => data_reg1,
               fdata1_in => mux5_out,
               fdata2_in => data_wr,
               fu_ctl => fu_mux4_ctl,
               data_out => mux4_out
               );
               
   alu_register: component reg   
	   port map(D => alu_result,
	            Q => alu_reg_out,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );
	                                             
	data_store_reg: component reg   
	   port map(D => mux4_out,
	            Q => data_out,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );	
	             	                                                          
	data_wr_reg: component reg   
	   port map(D => mux5_out,
	            Q => data_wr,
	            rst => rst, 
	            clk => clk, 
	            we => '1'
	            );
	            
	mux5: component mux56 
      port map(data0_in => alu_reg_out,
               data1_in => data_in,
               ctl => cu_mux5_ctl_d,
               data_out => mux5_out
               );  
                    
   --process (data_out)
      -- begin
   --if cu_mem_re_d = '1' then 
     --  data <= data_out;
   --else 
      -- data <= (others  => 'Z');
   --end if ;
   
   --end process;
  end;