addpc.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

--operate pc with jump and branch instruction
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mips_pack.all;


entity pcalu is
	port (mux3_in: in std_ulogic_vector(31 downto 0);
	      pc_in: in std_ulogic_vector(31 downto 0);
	      pc_ctl: in std_ulogic;
	      pc_out: out std_ulogic_vector(31 downto 0)
	     );
end entity pcalu;


architecture pcjump of pcalu is
    signal mux3_in_u,pc_in_u,pc_out_u: unsigned(31 downto 0);
begin
    mux3_in_u<=unsigned(mux3_in);
    pc_in_u<=unsigned(pc_in);
	ALU: process (mux3_in_u, pc_in_u, pc_ctl, pc_out_u) is
	begin
		case pc_ctl is
			when PC_JUMP => 
				pc_out_u <= mux3_in_u;
			when PC_BRANCH =>
				pc_out_u <= pc_in_u+mux3_in_u;
			when others =>
				pc_out_u<=pc_in_u;
		end case;
		pc_out<=std_ulogic_vector(pc_out_u);
	end process ALU;
end architecture pcjump;