alu.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

-- alu.vhdl
--
-- Main arithmetic logic unit
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mips_pack.all;


entity alu is
	port (mux1_in: in std_ulogic_vector(31 downto 0);
	      mux2_in: in std_ulogic_vector(31 downto 0);
	      alu_ctl: in std_ulogic_vector(5 downto 0);
	      alu_shamt: in std_ulogic_vector(4 downto 0);
	      alu_result: out std_ulogic_vector(31 downto 0);
	      --z_out: out std_ulogic;
	      --s_out: out std_ulogic;
	      of_out: out std_ulogic
	     );
end entity alu;


architecture a1 of alu is
	-- Internally treat values as unsigned
	signal mux1_in_u, mux2_in_u,alu_result_l,alu_result_r, alu_result_u: unsigned(31 downto 0);
begin
	-- Convert std_ulogic_vectors to unsigned and vice-versa
	mux1_in_u <= unsigned(mux1_in);
	mux2_in_u <= unsigned(mux2_in);
	alu_result <= std_ulogic_vector(alu_result_u);
	with alu_shamt(4 downto 0) select
	             alu_result_l <= mux2_in_u(31 downto 0) when "00000",
	                            mux2_in_u(30 downto 0)&"0" when "00001",
	                            mux2_in_u(29 downto 0)&"00" when "00010",
	                            mux2_in_u(28 downto 0)&"000" when "00011",
	                            mux2_in_u(27 downto 0)&"0000" when "00100",
	                            mux2_in_u(26 downto 0)&"00000" when "00101",
	                            mux2_in_u(25 downto 0)&"000000" when "00110",
	                            mux2_in_u(24 downto 0)&"0000000" when "00111",
	                            mux2_in_u(23 downto 0)&"00000000" when "01000",
	                            mux2_in_u(22 downto 0)&"000000000" when "01001",
	                            mux2_in_u(21 downto 0)&"0000000000" when "01010",
	                            mux2_in_u(20 downto 0)&"00000000000" when "01011",
	                            mux2_in_u(19 downto 0)&"000000000000" when "01100",
	                            mux2_in_u(18 downto 0)&"0000000000000" when "01101",
	                            mux2_in_u(17 downto 0)&"00000000000000" when "01110",
	                            mux2_in_u(16 downto 0)&"000000000000000" when "01111",
	                            mux2_in_u(15 downto 0)&"0000000000000000" when "10000",
	                            mux2_in_u(14 downto 0)&"00000000000000000" when "10001",
	                            mux2_in_u(13 downto 0)&"000000000000000000" when "10010",
	                            mux2_in_u(12 downto 0)&"0000000000000000000" when "10011",
	                            mux2_in_u(11 downto 0)&"00000000000000000000" when "10100",
	                            mux2_in_u(10 downto 0)&"000000000000000000000" when "10101",
	                            mux2_in_u(9 downto 0)&"0000000000000000000000" when "10110",
	                            mux2_in_u(8 downto 0)&"00000000000000000000000" when "10111",
	                            mux2_in_u(7 downto 0)&"000000000000000000000000" when "11000",
	                            mux2_in_u(6 downto 0)&"0000000000000000000000000" when "11001",
	                            mux2_in_u(5 downto 0)&"00000000000000000000000000" when "11010",
	                            mux2_in_u(4 downto 0)&"000000000000000000000000000" when "11011",
	                            mux2_in_u(3 downto 0)&"0000000000000000000000000000" when "11100",
	                            mux2_in_u(2 downto 0)&"00000000000000000000000000000" when "11101",
	                            mux2_in_u(1 downto 0)&"000000000000000000000000000000" when "11110",
	                            mux2_in_u(0)&"0000000000000000000000000000000" when "11111",
	                            mux2_in_u(31 downto 0) when others;

   with alu_shamt select
	             alu_result_r <=mux2_in_u(31 downto 0) when "00000",
	                            "0"&mux2_in_u(31 downto 1) when "00001",
	                            "00"&mux2_in_u(31 downto 2) when "00010",
	                            "000"&mux2_in_u(31 downto 3)when "00011",
	                            "0000"&mux2_in_u(31 downto 4)when "00100",
	                            "00000"&mux2_in_u(31 downto 5)when "00101",
	                            "000000"&mux2_in_u(31 downto 6)when "00110",
	                            "0000000"&mux2_in_u(31 downto 7)when "00111",
	                            "00000000"&mux2_in_u(31 downto 8)when "01000",
	                            "000000000"&mux2_in_u(31 downto 9)when "01001",
	                            "0000000000"&mux2_in_u(31 downto 10)when "01010",
	                            "00000000000"&mux2_in_u(31 downto 11) when "01011",
	                            "000000000000"&mux2_in_u(31 downto 12)when "01100",
	                            "0000000000000"&mux2_in_u(31 downto 13)when "01101",
	                            "00000000000000"&mux2_in_u(31 downto 14)when "01110",
	                            "000000000000000"&mux2_in_u(31 downto 15)when "01111",
	                            "0000000000000000"&mux2_in_u(31 downto 16)when "10000",
	                            "00000000000000000"&mux2_in_u(31 downto 17)when "10001",
	                            "000000000000000000"&mux2_in_u(31 downto 18)when "10010",
	                            "0000000000000000000"&mux2_in_u(31 downto 19)when "10011",
	                            "00000000000000000000"&mux2_in_u(31 downto 20) when "10100",
	                            "000000000000000000000"&mux2_in_u(31 downto 21)when "10101",
	                            "0000000000000000000000"&mux2_in_u(31 downto 22)when "10110",
	                            "00000000000000000000000"&mux2_in_u(31 downto 23) when "10111",
	                            "000000000000000000000000"&mux2_in_u(31 downto 24)when "11000",
	                            "0000000000000000000000000"&mux2_in_u(31 downto 25)when "11001",
	                            "00000000000000000000000000"&mux2_in_u(31 downto 26) when "11010",
	                            "000000000000000000000000000"&mux2_in_u(31 downto 27) when "11011",
	                            "0000000000000000000000000000"&mux2_in_u(31 downto 28)when "11100",
	                            "00000000000000000000000000000"&mux2_in_u(31 downto 29)when "11101",
	                            "000000000000000000000000000000"&mux2_in_u(31 downto 30) when "11110",
	                            "0000000000000000000000000000000"&mux2_in_u(31) when "11111",
	                            mux2_in_u(31 downto 0) when others;

	ALU: process (alu_ctl, alu_result_l,alu_result_r, mux1_in_u, mux2_in_u) is

	   variable tmp: unsigned(31 downto 0);
	begin
		-- default values
		alu_result_u <= (others => '-');
		of_out<='0';
		case alu_ctl is
			when ADDIU =>
				alu_result_u <= mux1_in_u + mux2_in_u;
			when ADD => 
				alu_result_u <= mux1_in_u + mux2_in_u;
				of_out<=(alu_result_u(31) xor mux1_in_u(31))and(alu_result_u(31) xor mux2_in_u(31));
         when ADDU => 
				alu_result_u <= mux1_in_u + mux2_in_u;
			when ADDI => 
				alu_result_u <= mux1_in_u + mux2_in_u;
				of_out<=(alu_result_u(31) xor mux1_in_u(31))and(alu_result_u(31) xor mux2_in_u(31));
			when SUBU =>
				alu_result_u <= mux1_in_u - mux2_in_u;
			when SSLL => 
			   alu_result_u<=alu_result_l;
		   when SSRA => 
		      alu_result_u<=alu_result_r;			    
			when LW =>
			   alu_result_u<=mux1_in_u+mux2_in_u; 	
			when LBU =>
			   alu_result_u<=mux1_in_u+mux2_in_u;
			when SW =>
			   alu_result_u<=mux1_in_u+mux2_in_u; 
			when SB =>
			   alu_result_u<=mux1_in_u+mux2_in_u;
			when LUI =>
			   alu_result_u<= mux2_in_u(15 downto 0)&"0000000000000000"; 
         when SLT =>            
            tmp := mux1_in_u-mux2_in_u;
            alu_result_u <= X"0000000"&"000"&tmp(31);
         when JAL =>
             alu_result_u<=mux1_in_u;
         when JUMP =>
             null;
         when JR =>
             null;
         when NOP =>
             null;
			when others => 
				null;
		end case;
	end process ALU;
	
	-- Zero flag
	--z_out <= '1' when alu_result_u = "00000000000000000000000000000000" else '0';
	--sign flag
   --s_out<='1' when alu_result_u(31) = '0' else '0';
end architecture a1;