register.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

-- reg.vhdl
--
-- N bit rising edge triggered register with asynchronous reset and clock
-- enable.
-- 
-- N = 32 bit by default
--
-- 1.2 [dsulli] added ce input (clock enable)
-- 1.3 [dsulli] changed ce to we (write enable)
library ieee;
use ieee.std_logic_1164.all;

entity reg is
	generic (H_L: std_ulogic := '1';
	         N: positive := 32;
	         RST_DATA: std_ulogic_vector(31 downto 0) :=X"00000000"
	         );
	port (D: in std_ulogic_vector (N-1 downto 0);
	    	 Q: out std_ulogic_vector (N-1 downto 0);
	    	 rst: in std_ulogic;
	      clk: in std_ulogic;
	      we: in std_ulogic
	     );
end entity reg;


architecture a1 of reg is
begin
	REG: process (rst, clk) is
	begin
		if rst = '1' then
			Q <= RST_DATA;
		elsif clk'event and clk = H_L then
			if we = '1' then
				Q <= D;
			end if;
		end if;
	end process REG;
end architecture a1;