mips_pack.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

library ieee;
use ieee.std_logic_1164.all;

package mips_pack is

component reg is
generic (H_L: std_ulogic := '1';
         N: positive := 32;
         RST_DATA: std_ulogic_vector(31 downto 0) :=X"00000000"
         );
port (D: in std_ulogic_vector (N-1 downto 0);
   clk: in std_ulogic;
   we: in std_ulogic;
   rst: in std_ulogic;
   Q: out std_ulogic_vector (N-1 downto 0)
  );
end component reg;

-- ALU operations
constant NOP: std_ulogic_vector(5 downto 0) := "000000"; 
constant ADDU: std_ulogic_vector(5 downto 0) := "100001"; 
constant ADD: std_ulogic_vector(5 downto 0) := "100000";  
constant SUBU: std_ulogic_vector(5 downto 0) := "001100"; 
constant SSLL: std_ulogic_vector(5 downto 0) := "001010";   --10
constant SSRA: std_ulogic_vector(5 downto 0) := "001011";   --11
constant SLT: std_ulogic_vector(5 downto 0) := "101010";   
constant LUI: std_ulogic_vector(5 downto 0) := "001111";   --15
constant LW: std_ulogic_vector(5 downto 0) := "100011";    
constant SW: std_ulogic_vector(5 downto 0) := "101011";    
constant LBU: std_ulogic_vector(5 downto 0) := "100100";  
constant SB: std_ulogic_vector(5 downto 0) := "101000";   
constant ADDI: std_ulogic_vector(5 downto 0) := "001000"; --8
constant ADDIU: std_ulogic_vector(5 downto 0) := "001001";--9
constant BEQ: std_ulogic_vector(5 downto 0) := "000100";--4
constant BNE: std_ulogic_vector(5 downto 0) := "000101"; --5
constant BGTZ: std_ulogic_vector(5 downto 0) := "000111";--7
constant BLTZ: std_ulogic_vector(5 downto 0) := "000001";--1
constant JUMP: std_ulogic_vector(5 downto 0) := "000010";--2
constant JR: std_ulogic_vector(5 downto 0) := "000110";   --6
constant JAL: std_ulogic_vector(5 downto 0) := "000011";  --3

--branch operations
constant BR_NOP: std_ulogic_vector(2 downto 0) := "000";
constant BR_BEQ: std_ulogic_vector(2 downto 0) := "100";
constant BR_BNE: std_ulogic_vector(2 downto 0) := "101";
constant BR_BGTZ: std_ulogic_vector(2 downto 0) := "111";
constant BR_BLTZ: std_ulogic_vector(2 downto 0) := "001";
constant BR_JUMP: std_ulogic_vector(2 downto 0) := "010";
constant BR_JR: std_ulogic_vector(2 downto 0) := "110";
constant BR_JAL: std_ulogic_vector(2 downto 0) := "011";

-- PC ALU operations
constant PC_NOP: std_ulogic := '0';
constant PC_JUMP: std_ulogic := '0';
constant PC_BRANCH: std_ulogic := '1';

-- AUX operations
--constant AUX_UNCHANGED: std_ulogic_vector(1 downto 0) := "00";
--constant LOAD_IMM: std_ulogic_vector(1 downto 0) := "01";
--constant LOAD_REG: std_ulogic_vector(1 downto 0) := "11";

end package mips_pack;