mux3.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

library ieee;
use ieee.std_logic_1164.all;
use work.mips_pack.all;

entity mux_3 is
   port (data0_in: in std_ulogic_vector (31 downto 0);
         data1_in: in std_ulogic_vector (31 downto 0);
         data2_in: in std_ulogic_vector (31 downto 0);
         cu_ctl: in std_ulogic_vector(1 downto 0);
         data_out: out std_ulogic_vector (31 downto 0)
         );
end entity mux_3;


architecture behavior of mux_3 is
begin

process(cu_ctl,data0_in,data1_in,data2_in)
    begin
 --combinational logic for next  value
--data_out <= fdata1_in when (fu_ctl = "01") else
--fdata2_in when (fu_ctl = "10") else 
--data0_in when (fu_ctl = "00") and (cu_ctl = '0') else 
--data1_in when (fu_ctl = "00") and (cu_ctl = '1') else
--(others => '-');
case cu_ctl is 
    when "00" =>
        data_out <= data0_in;
    when "01" =>
        data_out <= data1_in;
    when "10" =>
        data_out <= data2_in;
    when others =>
        data_out <= (others=> '-');
end case;
end process;

end architecture behavior;