test.vhd

modelsim+dc开发的4级流水线结构的MIPS CPU

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   13:44:00 01/12/2008
-- Design Name:   cpu
-- Module Name:   cpu
-- Project Name:  mips
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ModelSim for module: cpu
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.mips_pack.all;

entity test is
end test;

architecture behavior of test is 

--constant data
type dat is array(0 to 15) of std_ulogic_vector(31 downto 0);
constant dataram : dat := (
--a[0]-a[15]	X"209A0"
X"0000000D",
X"000001B3",
X"000001F6",
X"FFFFFFEA",
X"0000001F",
X"0000011A",
X"000002DD",
X"00000007",
X"000001F6",
X"00000040",
X"0000000B",
X"00000056",
X"FFFFFD7B",
X"0000006F",
X"00000009",
X"00000025"
);

type dat2 is array(0 to 139) of std_ulogic_vector(31 downto 0);
constant instram : dat2 := (
--Main  X"20000"
X"27BDFF90",
X"AFBF006C",
X"AFBE0068",
X"00000000",
X"03A0F021",
X"24020010",
X"AFC20010",
X"27C20018",
X"3C038002",
X"246309A0",
X"00402021",
X"0C00825A",
X"00602821",
X"24060040",
X"8FC20010",
X"00000000",
X"00021843",
X"AFC30060",
X"8FC20060",
X"00000000",
X"1C400003",
X"00000000",
X"08008076",
X"00000000",
X"8FC20060",
X"00000000",
X"AFC2005C",
X"8FC2005C",
X"8FC30010",
X"00000000",
X"0043102A",
X"14400003",
X"00000000",
X"08008071",
X"00000000",
X"8FC2005C",
X"00000000",
X"00401821",
X"00031080",
X"27C30010",
X"00431021",
X"24430008",
X"8C620000",
X"00000000",
X"AFC20064",
X"8FC2005C",
X"8FC30060",
X"00000000",
X"00431023",
X"AFC20058",
X"8FC20058",
X"00000000",
X"04400010",
X"00000000",
X"8FC20058",
X"00000000",
X"00401821",
X"00031080",
X"27C30010",
X"00431021",
X"24430008",
X"8C620000",
X"8FC30064",
X"00000000",
X"0062102A",
X"14400005",
X"00000000",
X"08008045",
X"00000000",
X"08008060",
X"00000000",
X"8FC20058",
X"8FC30060",
X"00000000",
X"00431021",
X"00401821",
X"00031080",
X"27C40010",
X"00441821",
X"24620008",
X"8FC30058",
X"00000000",
X"00602021",
X"00041880",
X"27C40010",
X"00641821",
X"24640008",
X"8C830000",
X"00000000",
X"AC430000",
X"8FC20058",
X"8FC30060",
X"00000000",
X"08008032",-- j
X"00431023",
X"AFC20058",
X"8FC20058",
X"8FC30060",
X"00000000",
X"00431021",
X"00401821",
X"00031080",
X"27C30010",
X"00431021",
X"24430008",
X"8FC20064",
X"00000000",
X"AC620000",
X"8FC2005C",
X"00000000",
X"0800801B",
X"24430001",
X"AFC3005C",
X"8FC20060",
X"00000000",
X"08008012",
X"00021843",
X"AFC30060",
X"03C0E821",
X"8FBF006C",
X"03E00008",
X"8FBE0068",
X"27BD0070",
X"00000000",
X"00000000",
X"00000000",--126

--Memcpy	 X"20968"
X"00041020",--127
X"10C00009",
X"00000000",
X"90A80000",
X"00000000",
X"A0880000",
X"20840001",
X"20A50001",
X"0800825B",--
X"20C6FFFF",
X"00000000",
X"03E00008",
X"00000000",
X"00000000"	--140
);
-------------------------------------------------------

----test 

--------------------------------------------------------
	-- Component Declaration for the Unit Under Test (UUT)
component cpu is
    port(rst: in std_ulogic;
			clk: in std_ulogic;
			--instruction pin
         ins: in std_ulogic_vector(31 downto 0);
         iaddr: out std_ulogic_vector(31 downto 0);
     			ird: out std_ulogic;
     			--data pin
         data_in: in std_ulogic_vector(31 downto 0);
     			data_out: out std_ulogic_vector(31 downto 0);
         daddr: out std_ulogic_vector(31 downto 0);
         drd: out std_ulogic;
			dwr: out std_ulogic;
			sel: out std_ulogic
			);
end component;

	--Inputs
	SIGNAL rst :  std_ulogic := '1';
	SIGNAL clk :  std_ulogic := '0';
	SIGNAL instruction :  std_ulogic_vector(31 downto 0) := (others=>'0');
	SIGNAL data_in :  std_ulogic_vector(31 downto 0) := (others=>'Z');

	--Outputs
	SIGNAL instr_addr_32 :  std_ulogic_vector(31 downto 0);
	SIGNAL instr_rd :  std_ulogic;
	SIGNAL data_addr_32 :  std_ulogic_vector(31 downto 0);
	SIGNAL data_rd :  std_ulogic;
	SIGNAL data_out :  std_ulogic_vector(31 downto 0);
	SIGNAL data_wr :  std_ulogic;
	signal data_size : std_ulogic;
	signal data_addr, instr_addr : std_logic_vector(17 downto 0);
	signal data_addr_u , instr_addr_u : std_ulogic_vector(17 downto 0);
---------------------------------
--  209A0 ~  	 --
--  20000 ~   --
--	 20968 ~    --
--  1FF80 ~ 	 --	
---------------------------------
   function conv_std_logic(i :std_ulogic) return std_logic is 
   variable j: std_logic;
   begin
       if(i = '1') then
           j := '1';
       else
           j := '0';
       end if;
       return j;
   end conv_std_logic; 
   function conv_std_logic_vector(i :std_ulogic_vector(17 downto 0)) return std_logic_vector is 
   variable j: std_logic_vector(17 downto 0);
   begin
       for n in 0 to 17 loop
           j(n) := conv_std_logic(i(n));
       end loop;
       return j;
   end conv_std_logic_vector;
	type memory is array(0 to 4095) of std_ulogic_vector(7 downto 0);

	signal data_ram: memory;
	signal instr_ram: memory;

	constant base_data : std_logic_vector(17 downto 0) := "10" & X"09A0";
	constant base_main : std_logic_vector(17 downto 0) := "10" & X"0000";
	constant base_memcpy : std_logic_vector(17 downto 0) := "10" & X"0968";
	constant base_stack : std_logic_vector(17 downto 0) := "01" & X"FF80";

	signal data0,data1,data2,data3,data4,data5,data6,data7,data8,data9,data10,data11,data12,data13,data14,data15 : std_ulogic_vector(31 downto 0);
BEGIN
   data_addr_u <= data_addr_32(17 downto 0);
   instr_addr_u <= instr_addr_32(17 downto 0);
   data_addr <= conv_std_logic_vector(data_addr_u);
	instr_addr <= conv_std_logic_vector(instr_addr_u);   
	data0(7 downto 0) <= data_ram(24);
	data0(15 downto 8) <= data_ram(25);
	data0(23 downto 16) <= data_ram(26);
	data0(31 downto 24) <= data_ram(27);
	data1(7 downto 0) <= data_ram(28);
	data1(15 downto 8) <= data_ram(29);
	data1(23 downto 16) <= data_ram(30);
	data1(31 downto 24) <= data_ram(31);
	data2(7 downto 0) <= data_ram(32);
	data2(15 downto 8) <= data_ram(33);
	data2(23 downto 16) <= data_ram(34);
	data2(31 downto 24) <= data_ram(35);
	data3(7 downto 0) <= data_ram(36);
	data3(15 downto 8) <= data_ram(37);
	data3(23 downto 16) <= data_ram(38);
	data3(31 downto 24) <= data_ram(39);
	data4(7 downto 0) <= data_ram(40);
	data4(15 downto 8) <= data_ram(41);
	data4(23 downto 16) <= data_ram(42);
	data4(31 downto 24) <= data_ram(43);
	data5(7 downto 0) <= data_ram(44);
	data5(15 downto 8) <= data_ram(45);
	data5(23 downto 16) <= data_ram(46);
	data5(31 downto 24) <= data_ram(47);
	data6(7 downto 0) <= data_ram(48);
	data6(15 downto 8) <= data_ram(49);
	data6(23 downto 16) <= data_ram(50);
	data6(31 downto 24) <= data_ram(51);
	data7(7 downto 0) <= data_ram(52);
	data7(15 downto 8) <= data_ram(53);
	data7(23 downto 16) <= data_ram(54);
	data7(31 downto 24) <= data_ram(55);
	data8(7 downto 0) <= data_ram(56);
	data8(15 downto 8) <= data_ram(57);
	data8(23 downto 16) <= data_ram(58);
	data8(31 downto 24) <= data_ram(59);
	data9(7 downto 0) <= data_ram(60);
	data9(15 downto 8) <= data_ram(61);
	data9(23 downto 16) <= data_ram(62);
	data9(31 downto 24) <= data_ram(63);
	data10(7 downto 0) <= data_ram(64);
	data10(15 downto 8) <= data_ram(65);
	data10(23 downto 16) <= data_ram(66);
	data10(31 downto 24) <= data_ram(67);
	data11(7 downto 0) <= data_ram(68);
	data11(15 downto 8) <= data_ram(69);
	data11(23 downto 16) <= data_ram(70);
	data11(31 downto 24) <= data_ram(71);
	data12(7 downto 0) <= data_ram(72);
	data12(15 downto 8) <= data_ram(73);
	data12(23 downto 16) <= data_ram(74);
	data12(31 downto 24) <= data_ram(75 );
	data13(7 downto 0) <= data_ram(76);
	data13(15 downto 8) <= data_ram(77);
	data13(23 downto 16) <= data_ram(78);
	data13(31 downto 24) <= data_ram(79);
	data14(7 downto 0) <= data_ram(80);
	data14(15 downto 8) <= data_ram(81);
	data14(23 downto 16) <= data_ram(82);
	data14(31 downto 24) <= data_ram(83);
	data15(7 downto 0) <= data_ram(84);
	data15(15 downto 8) <= data_ram(85);
	data15(23 downto 16) <= data_ram(86);
	data15(31 downto 24) <= data_ram(87);
	--"100000100110100000"when data_addr_32(17 downto 0) = "100000100110100000" else
	clk <= not clk after 50 ns;
	-- Instantiate the Unit Under Test (UUT)
	uut: component cpu 
    port map(rst => rst,
			   clk => clk,
			   --instruction pin
            ins => instruction,
            iaddr => instr_addr_32,
     			   ird => instr_rd,
     			   --data pin
            data_in => data_in,
            data_out => data_out,
            daddr => data_addr_32,
            drd => data_rd,
			   dwr => data_wr,
			   sel => data_size
			   );

	--data <=data_in when data_rd = '1' else  
	       --(others => 'Z');

	tb : PROCESS
	BEGIN

		-- Wait 200 ns for global reset to finish
		wait for 200 ns;
		rst <= '0';
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;
-------------------------------------
--  26A10 ~  26A37   28H   40	 10  --
--  20000 ~  201BF	1C0H	448 112 --
--	 21CE8 ~  21D1F   38H	56  14  --
-------------------------------------


	---------------data_ram----------------------
	P1:	process(rst,clk,data_out,data_wr,data_addr,data_size)
     	variable dadr : std_logic_vector(17 downto 0);
		variable tmp : std_ulogic_vector(31 downto 0);
		variable index: integer;
   begin
       index := conv_integer(data_addr-base_stack);
       if rst = '1' then 
		  		-------------------------------------------------------- 
		  		           --  --data_ram initializing--  --
   		     data_ram <= (others => (others => '0'));
       		  dadr := base_data;
			  for i in 0 to 15 loop
          		   tmp := dataram(i);
					data_ram(conv_integer(dadr-base_stack)) <= tmp(7 downto 0);
					data_ram(conv_integer(dadr-base_stack) + 1) <= tmp(15 downto 8);
       			     data_ram(conv_integer(dadr-base_stack) + 2) <= tmp(23 downto 16);
					data_ram(conv_integer(dadr-base_stack) + 3) <= tmp(31 downto 24);
					dadr := dadr + 4;
			   end loop;
				--------------------------------------------------------
				
				--------------------------------------------------------
       	elsif rising_edge(clk) then
		  ----------------------------------------------------------------------		
				-------------------------data_ram write---------------------------
				if data_wr = '1'  then
				    if index >= 0 and index < 4096 then 
				    if data_size = '1' then 
            			 data_ram(conv_integer(data_addr-base_stack)) <= data_out(7 downto 0);
            			 data_ram(conv_integer(data_addr-base_stack) + 1) <= data_out(15 downto 8);
            			 data_ram(conv_integer(data_addr-base_stack) + 2) <= data_out(23 downto 16);
					 data_ram(conv_integer(data_addr-base_stack) + 3) <= data_out(31 downto 24);
					 else
					 data_ram(conv_integer(data_addr-base_stack)) <= data_out(7 downto 0);
					 end if;
					 end if;
				end if;
        	end if;
   end process P1;
   	
   P2:	process(rst,data_rd,data_addr,data_size,data_ram) -- data_ram read
       variable index: integer;
   begin
         index := conv_integer(data_addr-base_stack);
         data_in <= (others => '-');
			if rst = '1' then 
				data_in <= (others => '0');		
			elsif data_rd = '1' then	
			      if index >= 0 and index < 4096 then  		  	
					if data_size = '1' then	
						data_in(7 downto 0)   <= data_ram(conv_integer(data_addr-base_stack));
						data_in(15 downto 8)  <= data_ram(conv_integer(data_addr-base_stack) + 1);
						data_in(23 downto 16) <= data_ram(conv_integer(data_addr-base_stack) + 2);
						data_in(31 downto 24) <= data_ram(conv_integer(data_addr-base_stack) + 3);
					else
						data_in(7 downto 0)   <= data_ram(conv_integer(data_addr-base_stack));
					end if;
					else
					   data_in(31 downto 0) <= (others => '0');
					end if;
			end if;
	end process P2;

	P3:process(rst,instr_rd,instr_addr,instr_ram)
	-------------------instr_ram------------------------------
		variable dadr : std_logic_vector(17 downto 0);
		variable tmp : std_ulogic_vector(31 downto 0);
   begin
        instruction<= (others => '-');
        if rst = '1' then 
				instruction<= (others => '0');
				instr_ram <= (others => (others => '0'));
				---------------instr_ram initialize----------------------
				dadr := base_main;
				for i in 0 to 125 loop
					tmp := instram(i);
					instr_ram(conv_integer(dadr-base_stack)) <= tmp(7 downto 0);
					instr_ram(conv_integer(dadr-base_stack) + 1) <= tmp(15 downto 8);
       			     instr_ram(conv_integer(dadr-base_stack) + 2) <= tmp(23 downto 16);
					instr_ram(conv_integer(dadr-base_stack) + 3) <= tmp(31 downto 24);
					dadr := dadr + 4;
				end loop;
				--------------------------------------------------------
				dadr := base_memcpy;
				for i in 0 to 13 loop
					tmp := instram(i + 126);
					instr_ram(conv_integer(dadr-base_stack)) <= tmp(7 downto 0);
					instr_ram(conv_integer(dadr-base_stack) + 1) <= tmp(15 downto 8);
       			     instr_ram(conv_integer(dadr-base_stack) + 2) <= tmp(23 downto 16);
					instr_ram(conv_integer(dadr-base_stack) + 3) <= tmp(31 downto 24);
					dadr := dadr + 4;
				end loop;
				--------------------------------------------------------
				-------------------instruction read---------------------
        elsif instr_rd = '1' then
					if instr_addr < base_main then
						instruction <= (others => '0');					-- Nop
					elsif  (instr_addr >= base_main	and instr_addr < base_main + 504) or (instr_addr >= base_memcpy and instr_addr < base_memcpy + 56	)  then
						instruction(7 downto 0) <= instr_ram(conv_integer(instr_addr-base_stack));
						instruction(15 downto 8) <= instr_ram(conv_integer(instr_addr-base_stack)+1);
						instruction(23 downto 16) <= instr_ram(conv_integer(instr_addr-base_stack)+2);
						instruction(31 downto 24) <= instr_ram(conv_integer(instr_addr-base_stack)+3);
					else														  	-- Nop
						instruction <= (others => '0');
					end if;
			end if;		
   end process P3;

END;
  
--configuration test_cfg of test is
   --for behavior
   --end for;
--end test_cfg;