regfile.vhd

来自「modelsim+dc开发的4级流水线结构的MIPS CPU」· VHDL 代码 · 共 351 行

-- regfile.vhdl
--
-- Register file containing R0 to R31
--
-- 1.2 [dsulli] Updated for new reg component with CE, simplified logic
-- 1.3 [dsulli] changed ce to rwe (register write enable)
-- 1.4 [dsulli] added R0 and R1 output ports

library ieee;
use ieee.std_logic_1164.all;
use work.mips_pack.all;


entity regfile is
	port (reg_r1: in std_ulogic_vector(4 downto 0);
	      reg_r2: in std_ulogic_vector(4 downto 0);
	      reg_w: in std_ulogic_vector(4 downto 0);
	      data_in: in std_ulogic_vector(31 downto 0);
	      clk: in std_ulogic;
	      rst: in std_ulogic;
	      we: in std_ulogic;
	      data_out1: out std_ulogic_vector(31 downto 0);
	      data_out2: out std_ulogic_vector(31 downto 0)
	      );
end entity regfile;


architecture a1 of regfile is
	signal Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
	   Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15,
	   Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23,
	   Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31: std_ulogic_vector(31 downto 0);
	signal rwe: std_ulogic_vector(31 downto 0);
begin

 	-- There has got to be a better way to do this
	Reg0: component reg  generic map (H_L => '0',N => 32) 
	port map (D => data_in, Q => Q0, rst => rst, 
	                              clk => clk, we => '0');          
	Reg1: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q1, rst => rst, 
	                              clk => clk, we => rwe(1));
	Reg2: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q2, rst => rst, 
	                              clk => clk, we => rwe(2));
	Reg3: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q3, rst => rst, 
	                              clk => clk, we => rwe(3));
	Reg4: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q4, rst => rst, 
	                              clk => clk, we => rwe(4));
	Reg5: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q5, rst => rst, 
	                              clk => clk, we => rwe(5));
	Reg6: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q6, rst => rst, 
	                              clk => clk, we => rwe(6));
	Reg7: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q7, rst => rst, 
	                              clk => clk, we => rwe(7));
	Reg8: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q8, rst => rst, 
	                              clk => clk, we => rwe(8));
	Reg9: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q9, rst => rst, 
	                              clk => clk, we => rwe(9));
	Reg10: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q10, rst => rst, 
	                              clk => clk, we => rwe(10));
	Reg11: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q11, rst => rst, 
	                              clk => clk, we => rwe(11));
	Reg12: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q12, rst => rst, 
	                              clk => clk, we => rwe(12));
	Reg13: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q13, rst => rst, 
	                              clk => clk, we => rwe(13));
	Reg14: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q14, rst => rst, 
	                              clk => clk, we => rwe(14));
	Reg15: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q15, rst => rst, 
	                              clk => clk, we => rwe(15));
	Reg16: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q16, rst => rst, 
	                              clk => clk, we => rwe(16));
	Reg17: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q17, rst => rst, 
	                              clk => clk, we => rwe(17));
	Reg18: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q18, rst => rst, 
	                              clk => clk, we => rwe(18));
	Reg19: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q19, rst => rst, 
	                              clk => clk, we => rwe(19));
	Reg20: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q20, rst => rst, 
	                              clk => clk, we => rwe(20));
	Reg21: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q21, rst => rst, 
	                              clk => clk, we => rwe(21));
	Reg22: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q22, rst => rst, 
	                              clk => clk, we => rwe(22));
	Reg23: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q23, rst => rst, 
	                              clk => clk, we => rwe(23));
	Reg24: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q24, rst => rst, 
	                              clk => clk, we => rwe(24));
	Reg25: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q25, rst => rst, 
	                              clk => clk, we => rwe(25));
	Reg26: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q26, rst => rst, 
	                              clk => clk, we => rwe(26));
	Reg27: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q27, rst => rst, 
	                              clk => clk, we => rwe(27));
	Reg28: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q28, rst => rst, 
	                              clk => clk, we => rwe(28));
	Reg29: component reg generic map (H_L => '0',N => 32,RST_DATA => X"8001FFF0")
	port map (D => data_in, Q => Q29, rst => rst, 
	                              clk => clk, we => rwe(29));
	Reg30: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q30, rst => rst, 
	                              clk => clk, we => rwe(30));
	Reg31: component reg generic map (H_L => '0',N => 32)
	port map (D => data_in, Q => Q31, rst => rst, 
	                              clk => clk, we => rwe(31));                      
	REG_READ: process (reg_r1, reg_r2, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,Q8, Q9, 
	Q10, Q11, Q12, Q13, Q14, Q15,Q16, Q17, Q18, Q19, Q20, Q21, Q22, 
	Q23,Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31) is
	begin
		case reg_r1 is
			when "00000" =>
				data_out1 <= Q0;
			when "00001" =>
				data_out1 <= Q1;
			when "00010" =>
				data_out1 <= Q2;
			when "00011" =>
				data_out1 <= Q3;
			when "00100" =>
				data_out1 <= Q4;
			when "00101" =>
				data_out1 <= Q5;
			when "00110" =>
				data_out1 <= Q6;
			when "00111" =>
				data_out1 <= Q7;
			when "01000" =>
				data_out1 <= Q8;
			when "01001" =>
				data_out1 <= Q9;
			when "01010" =>
				data_out1 <= Q10;
			when "01011" =>
				data_out1 <= Q11;
			when "01100" =>
				data_out1 <= Q12;
			when "01101" =>
				data_out1 <= Q13;
			when "01110" =>
				data_out1 <= Q14;
			when "01111" =>
				data_out1 <= Q15;
			when "10000" =>
				data_out1 <= Q16;
			when "10001" =>
				data_out1 <= Q17;
			when "10010" =>
				data_out1 <= Q18;
			when "10011" =>
				data_out1 <= Q19;
			when "10100" =>
				data_out1 <= Q20;
			when "10101" =>
				data_out1 <= Q21;
			when "10110" =>
				data_out1 <= Q22;
			when "10111" =>
				data_out1 <= Q23;
			when "11000" =>
				data_out1 <= Q24;
			when "11001" =>
				data_out1 <= Q25;
			when "11010" =>
				data_out1 <= Q26;
			when "11011" =>
				data_out1 <= Q27;
			when "11100" =>
				data_out1 <= Q28;
			when "11101" =>
				data_out1 <= Q29;
			when "11110" =>
				data_out1 <= Q30;
			when "11111" =>
				data_out1 <= Q31;
			when others => null;
		end case;
		case reg_r2 is
			when "00000" =>
				data_out2 <= Q0;
			when "00001" =>
				data_out2 <= Q1;
			when "00010" =>
				data_out2 <= Q2;
			when "00011" =>
				data_out2 <= Q3;
			when "00100" =>
				data_out2 <= Q4;
			when "00101" =>
				data_out2 <= Q5;
			when "00110" =>
				data_out2 <= Q6;
			when "00111" =>
				data_out2 <= Q7;
			when "01000" =>
				data_out2 <= Q8;
			when "01001" =>
				data_out2 <= Q9;
			when "01010" =>
				data_out2 <= Q10;
			when "01011" =>
				data_out2 <= Q11;
			when "01100" =>
				data_out2 <= Q12;
			when "01101" =>
				data_out2 <= Q13;
			when "01110" =>
				data_out2 <= Q14;
			when "01111" =>
				data_out2 <= Q15;
			when "10000" =>
				data_out2 <= Q16;
			when "10001" =>
				data_out2 <= Q17;
			when "10010" =>
				data_out2 <= Q18;
			when "10011" =>
				data_out2 <= Q19;
			when "10100" =>
				data_out2 <= Q20;
			when "10101" =>
				data_out2 <= Q21;
			when "10110" =>
				data_out2 <= Q22;
			when "10111" =>
				data_out2 <= Q23;
			when "11000" =>
				data_out2 <= Q24;
			when "11001" =>
				data_out2 <= Q25;
			when "11010" =>
				data_out2 <= Q26;
			when "11011" =>
				data_out2 <= Q27;
			when "11100" =>
				data_out2 <= Q28;
			when "11101" =>
				data_out2 <= Q29;
			when "11110" =>
				data_out2 <= Q30;
			when "11111" =>
				data_out2 <= Q31;
			when others => null;
		end case;
	end process REG_READ;
	
	REG_WRITE: process (reg_w, we) is
	begin
		-- Default values for rwe
		rwe <= (others => '0');
		
		if we = '1' then
			case reg_w is
				when "00000" =>
					rwe(0) <= '1';
				when "00001" =>
					rwe(1) <= '1';
				when "00010" =>
					rwe(2) <= '1';
				when "00011" =>
					rwe(3) <= '1';
				when "00100" =>
					rwe(4) <= '1';
				when "00101" =>
					rwe(5) <= '1';
				when "00110" =>
					rwe(6) <= '1';
				when "00111" =>
					rwe(7) <= '1';
				when "01000" =>
					rwe(8) <= '1';
				when "01001" =>
					rwe(9) <= '1';
				when "01010" =>
					rwe(10) <= '1';
				when "01011" =>
					rwe(11) <= '1';
				when "01100" =>
					rwe(12) <= '1';
				when "01101" =>
					rwe(13) <= '1';
				when "01110" =>
					rwe(14) <= '1';
				when "01111" =>
					rwe(15) <= '1';
				when "10000" =>
					rwe(16) <= '1';
				when "10001" =>
					rwe(17) <= '1';
				when "10010" =>
					rwe(18) <= '1';
				when "10011" =>
					rwe(19) <= '1';
				when "10100" =>
					rwe(20) <= '1';
				when "10101" =>
					rwe(21) <= '1';
				when "10110" =>
					rwe(22) <= '1';
				when "10111" =>
					rwe(23) <= '1';
					when "11000" =>
					rwe(24) <= '1';
				when "11001" =>
					rwe(25) <= '1';
				when "11010" =>
					rwe(26) <= '1';
				when "11011" =>
					rwe(27) <= '1';
				when "11100" =>
					rwe(28) <= '1';
				when "11101" =>
					rwe(29) <= '1';
				when "11110" =>
					rwe(30) <= '1';
				when "11111" =>
					rwe(31) <= '1';
				when others => null;
			end case;
		end if;
	end process REG_WRITE;
end architecture a1;