ac97api.h

pxa270触摸屏驱动程序

} Ac97MixerRegUsageCategoryT ;

// One entry in usage and initialization values table for the
//  AC'97 mixer registers

typedef struct Ac97MixerRegUsageAndInitEntryS
{
    Ac97MixerRegUsageCategoryT  mixerRegUsage;
    UINT32                      mixerRegDefaultVal;
} Ac97MixerRegUsageAndInitEntryT;

// Defines permissible write-access to the target codec's mixer registers 
//   and contains the initialization values.
// Used mainly for initialization purposes.

typedef Ac97MixerRegUsageAndInitEntryT
                           Ac97MixerRegUsageAndInitTableT[AC97_NUM_MIXER_REGS];

/*
*******************************************************************************
    FIFO processing control, status and scratchpad structure
*******************************************************************************
*/

// In all cases
// Buffer size = 7680 bytes (1920 samples) (40 mSec at 48K 4-byte samples per 
//      second, longer for slower sample rates)

typedef struct Ac97FifoProcessingInfoS
{
    XsAc97CtrlFifoIdT fifoId; // Who am I?
    PCHAR   fifoNameStrP;     // Spell out who I am.  
    BOOL    isSupported;    // Is this FIFO supported in this implementation?
    VUINT32 isrError;       // For this FIFO
                            // Bit-map of errors and status for this FIFO, 
                            //  including both AC97 FIFO errors and DMA errors.
    VUINT32  fifoStatus;     //  Uses the "AC97_FIFO_ST_" constants.
    VINT     dmaRestarts;    // Zero is the good number.

    VUINT32  ac97FifoErrs;   // Count of FIFO errors reported by AC97 controller
    VUINT32  ac97DcsrBuserrIntrs; // Count of DCSR_BUSERRINTR status events
    VUINT32  ac97DcsrStartIntrs;  // Count of DCSR_STARTINTR status events
    VUINT32  ac97DcsrEndIntrs;    // Count of DCSR_ENDINTR status events
    VUINT32  ac97DcsrStopIntrs;   // Count of DCSR_STOPINTR status events

                            // For setting up callback with AC97 controller
    XsAc97CtrlIntIdT fifoInterruptId;

    XsDmaHandlerFnPT thisFifosDmaHandlerFnP;
                            // Needed for DMA configuration
    XsDmaDeviceNamesT  dmaDeviceName;
    INT     dmaChannel;     // Actual DMA channel assigned
                            // Requested DMA channel priority
    XsDmaChannelPriorityT  dmaChannelPrioReq;      
                            // Relative priority of the assigned DMA channel
                            //  compared with requested priority
    XsDmaChannelStatusT    dmaChannelPrioCmp;     
                            // Virtual address of active root descriptor in chain
    XsDmaDescriptorElementsTPT activeDescriptorRootP;  
                            // Virtual address of DMA Loop root descriptor
                            //  (buffers not SW readable or writable)
    XsDmaDescriptorElementsTPT dmaLoopDescriptorRootP;  
                            // Virtual address of standard mode root descriptor
                            //  (buffers are SW readable and writable)
    XsDmaDescriptorElementsTPT standardModeDescriptorRootP;
                            // Virtual address of special-purpose descriptor
                            //  for stopping DMA
    XsDmaDescriptorElementsTPT stopDescriptorRootP;
// ??@@@
                            // DMA descriptor whose buffer is currently
                            //  pointed to by the driver for read or write
    XsDmaDescriptorElementsTPT  dmaDescriptorCurrSwP;
                            // Physical address of the next descriptor to load,
                            //  as found in the DMA hardware.  Scratch usage.
    UINT32  dmaDescriptorHwPaddrNextTmp;
                            // Current pointer to client buffer header.  
                            //  Fields in buffer header will hold buffer
                            //  base pointer and read or write offset
    Ac97ClientDataBufHeaderT*  clientBufP;
                            // Total # 32-bit samples transferred between 
                            //  client and driver buffers this time for 
    INT32   samplesProcessed;  //  this FIFO.

                            // The callbacks that the AC97 codec module itself
                            //  registers with other modules expect a pointer
                            //  to an Ac97FifoProcessingInfoT structure.
                            // Having this member permits access to flags, etc.
                            //  in the context structure for the entire codec.
    Ac97ContextPT   parentAc97ctxP;    


// Are these members needed?
    BOOL    variableRateEnabled;
    INT32   rateRequested;  // Sample rate requested by the client or default.
    INT32   rateAchieved;   // Depends on codec capabilities, may not match req

}   Ac97FifoProcessingInfoT;

/*
*******************************************************************************
    AC97 Context structure definition
*******************************************************************************
*/

typedef struct Ac97ContextS
{
    UINT32  loggedError;            // In general for this driver
    UINT32  isrError;
    UINT16  codecId;              // Capabilities+primary...,(AC97_MR_EA_ID...)
    PCHAR   codecDeviceNameStrP;    // A descriptive name for the codec.
    CHAR    vendorIdString  [4];    // From mixer regs 0x7C + 0x7E
    INT     vendorRevNumber;        // From mixer reg 0x7E
    UINT32  audioCodecInUse;
    BOOL    audioCodecInitialized;
    BOOL    audioCodecReady;
    UINT32  audioCodecResetState;   // For power management use
    UINT32  modemCodecInUse;
    BOOL    modemCodecInitialized;
    BOOL    modemCodecReady;
    UINT32  modemCodecResetState;   // For power management use
    Ac97ServicesT* ApiServicesP;    // Pointer to func list for the API svcs
    //
    // Driver internal use.
    //
    XsAc97CtrlCodecModemIdT  audioIdForController; 
    XsAc97CtrlCodecModemIdT  modemIdForController;  
                                    // Power on defaults, touching all 
                                    //  permitted registers.
    Ac97MixerRegUsageAndInitTableT*  mixerRegsDfltValsUsageP;
    Ac97MixerRegsSpecialMasksT*      mixerRegsSpecialMasksP;
    UINT32  mixerRegsCurrVals [AC97_NUM_MIXER_REGS];    // Current values

    //
    //  DMA, buffer processing and variable rate information structures:
    //    One for each FIFO supported by the assumed controller
    //
    Ac97FifoProcessingInfoT fifoProcessingInfoRecords [XS_AC97CTRL_FIFO_NUM];
    Ac97DmaBufModeT dmaBufMode;

}  Ac97ContextT ;

//
// Now, declare/define the context structures
//

EXTRN Ac97ContextT  Ac97ContextCodec0;   // Primary codec
// No secondary codec in target platforms
// EXTRN Ac97ContextT  Ac97ContextCodec1;  // First Secondary codec


/*
*******************************************************************************
    Standard API Prototypes
*******************************************************************************
*/

void   Ac97SWInit  (void);                 // Primary and any secondary codecs

UINT32 Ac97HWSetup (Ac97ContextT* ctxP);   // Primary and any secondary codecs

/*
*******************************************************************************
    Low-level prototypes
*******************************************************************************
*/

UINT32 Ac97GetVendorIDandRev (Ac97ContextT* ctxP, PCHAR , PINT );

void Ac97SwRestoreDefaultsAudio (Ac97ContextT* );

UINT32 Ac97HwReconfigAudio (Ac97ContextT* );

UINT32 Ac97HwPowerOnAudioSubsystems (Ac97ContextT* );  // Stub

UINT32 Ac97HwShutdownAudioSubsystems (Ac97ContextT* );  // Stub@@@

void Ac97SwRestoreDefaultsModem (Ac97ContextT* );  // Stub

UINT32 Ac97HwReconfigModem (Ac97ContextT* );     // Stub

UINT32 Ac97HwShutdownModem (Ac97ContextT* );    // Stub

void Ac97SwSetDefaultsUcb1400 (Ac97ContextT* );


void   Ac97SwRestoreDefaultsAudio (Ac97ContextT* ctxP);
void   Ac97SwRestoreDefaultsModem (Ac97ContextT* ctxP);
void   Ac97SwSetDefaultsUcb1400 (Ac97ContextT* ctxP);

// @@ Ac97GeneralHwControlFnPT 
UINT32 Ac97HwReconfigAudio (Ac97ContextT* ctxP);
UINT32 Ac97PowerOnAudioSubsystems (Ac97ContextT* ctxP);
UINT32 Ac97ShutdownAudioSubsystems (Ac97ContextT* ctxP);

// @@ Ac97GetStereoSideValueFnPT 
UINT32 Ac97GetMasterVolLeft (Ac97ContextT* ctxP, PUINT8 attenuationP);
UINT32 Ac97GetMasterVolRight (Ac97ContextT* ctxP, PUINT8 attenuationP);
UINT32 Ac97GetRecordSelectLeft (Ac97ContextT* ctxP, PUINT8 inputSourceP);
UINT32 Ac97GetRecordSelectRight (Ac97ContextT* ctxP, PUINT8 inputSourceP);
UINT32 Ac97GetRecordGainLeft (Ac97ContextT* ctxP, PUINT8 gainP);
UINT32 Ac97GetRecordGainRight (Ac97ContextT* ctxP, PUINT8 gainP);

// @@ Ac97GetEnableFnPT 
UINT32 Ac97GetMasterVolMute (Ac97ContextT* ctxP, BOOL* muteEnableP);
UINT32 Ac97GetHWLoopAdcToDac (Ac97ContextT* ctxP, BOOL* enableLoopP);
UINT32 Ac97GetPcmVariableRateEnable (Ac97ContextT* ctxP, BOOL* enabledP);
UINT32 Ac97GetRecordGainMute (Ac97ContextT* ctxP, BOOL* muteEnableP);

// @@ Ac97SetStereoSideValueFnPT 
UINT32 Ac97SetMasterVolLeft (Ac97ContextT* ctxP, UINT8 attenuation);
UINT32 Ac97SetMasterVolRight (Ac97ContextT* ctxP, UINT8 attenuation);
UINT32 Ac97SetRecordSelectLeft (Ac97ContextT* ctxP, UINT8 inputSource);
UINT32 Ac97SetRecordSelectRight (Ac97ContextT* ctxP, UINT8 inputSource);
UINT32 Ac97SetRecordGainLeft (Ac97ContextT* ctxP, UINT8 gain);
UINT32 Ac97SetRecordGainRight (Ac97ContextT* ctxP,  UINT8 gain);

// @@ Ac97SetEnableFnPT 
UINT32 Ac97SetMasterVolMute (Ac97ContextT* ctxP, BOOL muteEnable);
UINT32 Ac97SetHWLoopAdcToDac (Ac97ContextT* ctxP, BOOL enableLoop);
UINT32 Ac97SetPcmVariableRateEnable (Ac97ContextT* ctxP, BOOL enable);
UINT32 Ac97SetRecordGainMute (Ac97ContextT* ctxP, BOOL muteEnable);

UINT32 Ac97GetSampleRatePcmOut (Ac97ContextT* ctxP, PUINT16 currentRateP);
UINT32 Ac97GetSampleRatePcmIn (Ac97ContextT* ctxP, PUINT16 currentRateP);

UINT32 Ac97SetSampleRatePcmOut (Ac97ContextT* ctxP, UINT16 desiredRate);
UINT32 Ac97SetSampleRatePcmIn (Ac97ContextT* ctxP, UINT16 desiredRate);



UINT32 Ac97GetVendorIDandRev (Ac97ContextT* ctxP, 
                              PCHAR         vendorIdStringP, 
                              PINT          vendorRevNumberP);
UINT32 Ac97GetAnyMixerRegister (Ac97ContextT*        ctxP, 
                                AC97MixerRegisterIdT targetReg, 
                                PUINT16              curRegValueP);
UINT32 Ac97SetAnyMixerRegister (Ac97ContextT*        ctxP, 
                                AC97MixerRegisterIdT targetReg, 
                                UINT16               newValue);

void Ac97ClearFifoStatus (Ac97FifoProcessingInfoT*);

UINT32 Ac97OpenFifoPcmIn    (Ac97ContextT*, Ac97FifoProcessingInfoT**);
UINT32 Ac97OpenFifoPcmOut   (Ac97ContextT*, Ac97FifoProcessingInfoT**);
UINT32 Ac97OpenFifoMicIn    (Ac97ContextT*, Ac97FifoProcessingInfoT**);
UINT32 Ac97OpenFifoModemIn  (Ac97ContextT*, Ac97FifoProcessingInfoT**);
UINT32 Ac97OpenFifoModemOut (Ac97ContextT*, Ac97FifoProcessingInfoT**);
UINT32 Ac97CloseFifo (Ac97FifoProcessingInfoT* fifoInfoP);
UINT32 Ac97StartFifo (Ac97FifoProcessingInfoT* );
UINT32 Ac97StopFifo (Ac97FifoProcessingInfoT* fifoInfoP);
UINT32 Ac97StopFifoQuick (Ac97FifoProcessingInfoT* fifoInfoP);


#if 0

/*
*******************************************************************************
    Notes
*******************************************************************************
*/

//
// Audio buffer sizes calculations:
// 4 bytes per stereo sample
// Some standard AC97 data rates, various buffer durations
//
//        K in cells of table is x 1000 bytes (not x 1024 bytes)
//        (1 second is for comparison only.  Max DMA buf size is 8191 bytes)
//        (Parentheses mean this size won't work: must be multiple of 4 bytes
//         and less than 8192 bytes.  Duration for buffer must be higher or 
//         lower.)    
//
//    Rate                     Duration 
// (1000 Hz)    1 Sec     10 ms     20 ms     25 ms     40 ms     50 ms 
// 
//    8.0       32   K     320       640       800      1280      1600
//   11.025     44.1 K    (441)     (882)    (1102.5)   1764     (2205)
//   16         64   K     640      1280      1600      2560      3200
//   22.05      88.2 K    (882)     1764     (2205)     3528     (4410)
//   32        128   K    1280      2560      3200      5120      6400 
//   44.1      176.4 K    1764      3528     (4410)     7056     (880)
//   48        192   K    1920      3840      4800      7680     (9600)  
// 
// Bufs per 10 sec:       1000       500       400       250       200
// 

#endif // #if 0

#undef EXTRN

#endif /*_AC97API_H */