ucb1400.h

pxa270触摸屏驱动程序

/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be construed as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document.
**  Except as permitted by such license, no part of this document may be
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation.
**
**  FILENAME:       Ucb1400.h
**
**  PURPOSE:        Define the UCB1400 Registers
**
**  LAST MODIFIED:  $Modtime: 7/17/03 1:01p $
******************************************************************************/

#ifndef _UCB1400_H
#define _UCB1400_H

// UCB1400 Register Definitions

#define UCB_RR      0x00    // Reset Register
#define UCB_MVR     0x02    // Master Volume Register
#define UCB_REG0X04 0x04    // Reserved
#define UCB_REG0X06 0x06    // Reserved
#define UCB_REG0X08 0x08    // Reserved
#define UCB_REG0X0A 0x0A    // Reserved
#define UCB_REG0X0C 0x0C    // Reserved
#define UCB_MICVR   0x0E    // MIC Volume Register
#define UCB_REG0X10 0x10    // Reserved
#define UCB_REG0X12 0x12    // Reserved
#define UCB_REG0X14 0x14    // Reserved
#define UCB_REG0X16 0x16    // Reserved
#define UCB_REG0X18 0x18    // Reserved
#define UCB_RSR     0x1A    // Record Select Register
#define UCB_RGR     0x1C    // Record Gain Register
#define UCB_REG0X1E 0x1E    // Reserved
#define UCB_GPR     0x20    // General Purpose Register
#define UCB_REG0X22 0x22    // Reserved
#define UCB_REG0X24 0x24    // Reserved
#define UCB_PCSR    0x26    // Powerdown Ctrl/Status Register
#define UCB_EAIDR   0x28    // Extended Audio ID Register
#define UCB_EASCR   0x2A    // Extended Audio Status/Ctrl Register
#define UCB_ADR     0x2C    // Audio DAC Sample Rate Register
#define UCB_REG0X2E 0x2E    // Reserved
#define UCB_REG0X30 0x30    // Reserved
#define UCB_AAR     0x32    // Audio ADC Sample Rate Register
#define UCB_REG0X34 0x34    // Reserved
#define UCB_REG0X36 0x36    // Reserved
#define UCB_REG0X38 0x38    // Reserved
#define UCB_REG0X3A 0x3A    // Reserved
#define UCB_REG0X3C 0x3C    // Reserved
#define UCB_REG0X3E 0x3E    // Reserved
#define UCB_REG0X40 0x40    // Reserved
#define UCB_REG0X42 0x42    // Reserved
#define UCB_REG0X44 0x44    // Reserved
#define UCB_REG0X46 0x46    // Reserved
#define UCB_REG0X48 0x48    // Reserved
#define UCB_REG0X4A 0x4A    // Reserved
#define UCB_REG0X4C 0x4C    // Reserved
#define UCB_REG0X4E 0x4E    // Reserved
#define UCB_REG0X50 0x50    // Reserved
#define UCB_REG0X52 0x52    // Reserved
#define UCB_REG0X54 0x54    // Reserved
#define UCB_REG0X56 0x56    // Reserved
#define UCB_REG0X58 0x58    // Reserved
#define UCB_IODR    0x5A    // I/O Data Register
#define UCB_IODIRR  0x5C    // I/O Direction Register
#define UCB_PIER    0x5E    // Positive INT Enable Register
#define UCB_NEIR    0x60    // Negative INT Enable Register
#define UCB_ICSR    0x62    // INT Clear/Status Register
#define UCB_TSCR    0x64    // Touch Screen Control Register
#define UCB_ADCCR   0x66    // ADC Control Register
#define UCB_ADCDR   0x68    // ADC Data Register
#define UCB_FCSR1   0x6A    // Feature CSR1 Register
#define UCB_FCSR2   0x6C    // Feature CSR2 Register
#define UCB_TCR     0x6E    // Test Control Register
#define UCB_REG0X70 0x70    // Reserved
#define UCB_REG0X72 0x72    // Reserved
#define UCB_REG0X74 0x74    // Reserved
#define UCB_REG0X76 0x76    // Reserved
#define UCB_REG0X78 0x78    // Reserved
#define UCB_REG0X7A 0x7A    // Reserved
#define UCB_VID1    0x7C    // Vendor ID1 Register
#define UCB_VID2    0x7E    // Vendor ID2 Register


// UCB Reset Register (RR) definitions

#define UCB_RR_LOUDNESS ( 0x1 << 5 )    // Loudness (bass boost) supported
#define UCB_RR_20BITDAC ( 0x1 << 7 )    // supports 20 bit DAC
#define UCB_RR_20BITADC ( 0x1 << 9 )    // supports 20 bit ADC

// Master Volume Register (MVR) definitions

#define UCB_MVR_MR_SHIFT    0               // Volume Right, 6 bits wide
// Bits 6,7 Reserved
#define UCB_MVR_ML_SHIFT    8               // Volume Left, 6 bits wide
// Bit 14 Reserved
#define UCB_MVR_MM          ( 0x1 << 15 )   // Master Mute

// MIC Volume Register (MCVR) definitions

// Bits 0-5 Reserved
#define UCB_MCVR_20DB       ( 0x1 << 6 )    // MIC Volume boosted by 20 dB
// Bits 7-15 Reserved

// Record Select Register (RSR) definitions

#define UCB_RSR_SR_SHIFT    0
#define UCB_RSR_SR_CL       ( 0x0 << UCB_RSR_SR_SHIFT ) // copy from left
#define UCB_RSR_SR_LINE     ( 0x100 << UCB_RSR_SR_SHIFT )

#define UCB_RSR_SL_SHIFT    8
#define UCB_RSR_SL_MIC      ( 0x0 << UCB_RSR_SL_SHIFT )
#define UCB_RSR_SL_LINE     ( 0x100 << UCB_RSR_SL_SHIFT )

// Record Gain Register (RGR) definitions

#define UCB_RGR_GR_SHIFT    0               // Gain Right, 4 bits wide
// Bits 4-7 Reserved
#define UCB_RGR_GL_SHIFT    8               // Gain Left, 4 bits wide
// Bits 12-14 Reserved
#define UCB_RGR_RM          ( 0x1 << 15 )   // Record Mute

// General Purpose Register (GPR) definitions

// Bits 0-6 Reserved
#define UCB_GPR_LPBK        ( 0x1 << 7 )    // ADC/DAC Loopback Mode
// Bits 8-15 Reserved

// Powerdown Control/Status Register (PCSR) definitions

#define UCB_PCSR_ADCR   ( 0x1 << 0 )    // ADC ready to transmit data
#define UCB_PCSR_DAC    ( 0x1 << 1 )    // DAC ready to accept data
// Bit 2 Reserved
#define UCB_PCSR_REF    ( 0x1 << 3 )    // Vref is up to nominal level
// Bits 4-7 Reserved
#define UCB_PCSR_PR0    ( 0x1 << 8 )    // ADC & input path powerdown
#define UCB_PCSR_PR1    ( 0x1 << 9 )    // DAC & ouput path powerdown
// Bit 10 Reserved
#define UCB_PCSR_PR3    ( 0x1 << 11 )   // Vref powerdown
#define UCB_PCSR_PR4    ( 0x1 << 12 )   // Digital interface powerdown
#define UCB_PCSR_PR5    ( 0x1 << 13 )   // Internal Clock disable
// Bits 14,15 Reserved

// Extended Audio ID Register (EAIDR) definitions

#define UCB_EAIDR_VRA   ( 0x1 << 0 )    // Variable Rate PCM Audio supported
// Bits 1-13 Reserved
#define UCB_EAIDR_ID    ( 0x11 << 14 )  // 2 bits wide, Always 0.  UCB1400 is a primary codec

// Extended Audio Status and Control Register (EASCR) definitions

#define UCB_EASCR_VRA   ( 0x1 << 0 )    // Enable Variable Rate Audio mode
// Bits 1-15 Reserved

// Audio DAC & ADC Sample Rate Control Register (ADR & AAR) definitions

#define UCB_DR_8000     0x1F40  //  8000 samples/sec
#define UCB_DR_11025    0x2B11  // 11025 samples/sec
#define UCB_DR_16000    0x3E80  // 16000 samples/sec
#define UCB_DR_22050    0x5622  // 22050 samples/sec
#define UCB_DR_32000    0x7D00  // 32000 samples/sec
#define UCB_DR_44100    0xAC44  // 44100 samples/sec
#define UCB_DR_48000    0xBB80  // 48000 samples/sec

// I/O Data Register (IODR) and I/O Data Direction (IODIRR) definitions
#define UCB_IO0 ( 0x1 << 0 )
#define UCB_IO1 ( 0x1 << 1 )
#define UCB_IO2 ( 0x1 << 2 )
#define UCB_IO3 ( 0x1 << 3 )
#define UCB_IO4 ( 0x1 << 4 )
#define UCB_IO5 ( 0x1 << 5 )
#define UCB_IO6 ( 0x1 << 6 )