ac97api.h

pxa270触摸屏驱动程序

*******************************************************************************
    Extended Audio mixer register (0x28 - 0x3A) constants
*******************************************************************************
*******************************************************************************
*/

/*
*******************************************************************************
    mixer reg 0x28 bits and bit fields
*******************************************************************************
*/
// Defines for (capability and id) bits in mixer reg 0x28
// Undefined bit positions (2, 4, 5, 10..13) are not given symbols.

#define AC97_MR_EA_ID_VRA       (1u << 0)  // Variable Rate PCM Audio support
#define AC97_MR_EA_ID_DRA       (1u << 1)  // Double Rate PCM Audio support
#define AC97_MR_EA_ID_VRM       (1u << 3)  // Variable Rate MIC input support
#define AC97_MR_EA_ID_CDAC      (1u << 6)  // PCM Center DAC support
#define AC97_MR_EA_ID_SDAC      (1u << 7)  // PCM Surround DAC support
#define AC97_MR_EA_ID_LDAC      (1u << 8)  // PCM LFE DAC support
#define AC97_MR_EA_ID_AMAP      (1u << 9)  // Slot/DAC mappings using Codec ID

#define AC97_MR_EA_ID_PRIM      (0u <<14)  // Primary Codec
#define AC97_MR_EA_ID_SEC       (1u <<14)  // Secondary Codec
#define AC97_MR_EA_ID_CODEC_MSK (3u <<14)  // Isolate Prim, Sec# ID info

#define AC97_MR_EA_ID_MSK       (OxC3CB)   // Mask for valid bits


// Defines for (status and control) bits in mixer reg 0x2A
// Undefined bit positions (2, 4, 5, 10, 15) are not given symbols.


// Read/write    
#define AC97_MR_EA_STAT_CTRL_VRA_ENAB (1u << 0)  // Variable Rate PCM Audio enable
#define AC97_MR_EA_STAT_CTRL_DRA_ENAB (1u << 1)  // Double Rate PCM Audio enable
#define AC97_MR_EA_STAT_CTRL_VRM_ENAB (1u << 3)  // Variable Rate MIC input enable

// Read-only
#define AC97_MR_EA_STAT_CTRL_CDAC_RDY (1u << 6)  // PCM Center DAC readiness
#define AC97_MR_EA_STAT_CTRL_SDAC_RDY (1u << 7)  // PCM Surround DAC readiness
#define AC97_MR_EA_STAT_CTRL_LDAC_RDY (1u << 8)  // PCM LFE DAC readiness
#define AC97_MR_EA_STAT_CTRL_MADC_RDY (1u << 9)  // MIC ADC readiness

// Read/write    
#define AC97_MR_EA_STAT_CTRL_PRI_ENAB (1u <<11)  // 1 = PCM Center DAC off
#define AC97_MR_EA_STAT_CTRL_PRJ_ENAB (1u <<12)  // 1 = PCM Surround DACs off
#define AC97_MR_EA_STAT_CTRL_PRK_ENAB (1u <<13)  // 1 = PCM LFE DAC off
#define AC97_MR_EA_STAT_CTRL_PRL_ENAB (1u <<14)  // 1 = MIC ADC off


#define AC97_MR_EA_STAT_CTRL_MSK      (Ox7BCB)   // Mask for valid bits
#define AC97_MR_EA_STAT_CTRL_WR_MSK   (Ox780B)   // Mask for writeable bits


/*
*******************************************************************************
    Miscellaneous constants
*******************************************************************************
*/

#define AC97_SET                         1
#define AC97_CLEAR                       0

                                        // For this controller, all sample 
                                        //  interfaces are 32-bits wide.  For 
                                        //  stereo data (PCM In/Out), the
                                        //  sample is a concatenation, with the 
#define AC97_BYTES_PER_SAMPLE      4    //  right channel being bits 31:16

// Standard buffer size = 7680  // (40 mSec at 48K 4-byte samples per second)
                                             // 11 full sine waves @ 440 Hz and 48000 sps
#define AC97_STANDARD_BUF_SIZE_BYTES   4800  //  with a 1000 sample sine wave: 25 ms = 1/40 sec

#define AC97_STANDARD_BUF_SIZE_SAMPLES  AC97_STANDARD_BUF_SIZE_BYTES \
                                        / AC97_BYTES_PER_SAMPLE

                                      // DMA can only do 8191 bytes- be careful
#define AC97_MAX_BUF_SIZE       8188  // Limit on what we use.

// Next definitions may not be needed here.  They are system and test program
//  issues, really. 
                                      // Maximum number of buffers in each 
#define AC97_MAX_BUFS            200  //  direction.  Limits demos somewhat.


// Reporting and local recording of errors that can the affect AC'97 Codec
//  logical FIFO handling.
//  Bit-mapped for packing into a status word.   Generally apply to a certain 
//  FIFO and are recorded in an Ac97FifoProcessingInfoT variable's 
//  fifoStatus member.

                                    // Number of restarts the AC97 tries for
                                    //  a DMA channel before quitting.
#define AC97_DMA_ERR_RESTARTS           3


typedef enum Ac97FifoStatShiftE
{
     // 0x00000100                     // Shifted value of 1u
    // Intrinsic FIFO characteristics
    AC97_FIFO_ST_DIR_TX_SHF            ,    // 0x00000001
    AC97_FIFO_ST_DMA_LP_ABLE_SHF       ,    // 0x00000002

    // Configurable characteristics
    AC97_FIFO_ST_DMA_LP_MODE_SHF   = 4 ,    // 0x00000010
    AC97_FIFO_ST_FIFO_ISR_MODE_SHF     ,    // 0x00000020
    AC97_FIFO_ST_DMA_ISR_MODE_SHF      ,    // 0x00000040

    // General operational status
    AC97_FIFO_ST_OPEN_SHF          = 8 ,    // 0x00000100
    AC97_FIFO_ST_ACTIVE_SHF            ,    // 0x00000200
    AC97_FIFO_ST_DMA_RUNNING_SHF       ,    // 0x00000400

    // Operations support status    
    AC97_FIFO_ST_FIFO_ISR_REG_SHF   =12,    // 0x00001000
    AC97_FIFO_ST_DMA_CHAN_ACQ_SHF      ,    // 0x00002000
    AC97_FIFO_ST_DMA_ISR_REG_SHF       ,    // 0x00004000

    // Event flags from ISRs, may be errors
    AC97_FIFO_ST_FIFO_ERR_SHF       =16,    // 0x00010000
    AC97_FIFO_ST_DCSR_BUSERRINTR_SHF   ,    // 0x00020000
    AC97_FIFO_ST_DCSR_STARTINTR_SHF    ,    // 0x00040000
    AC97_FIFO_ST_DCSR_ENDINTR_SHF      ,    // 0x00080000
    AC97_FIFO_ST_DCSR_STOPINTR_SHF     ,    // 0x00100000

    // Error states
    AC97_FIFO_ST_DMA_TOO_MANY_SHF   =24,    // 0x01000000
    AC97_FIFO_ST_DMA_CHAN_NA_SHF       ,    // 0x02000000
    AC97_FIFO_ST_INVALID_OP_SHF             // 0x04000000

} Ac97FifoStatShiftT;



                                    // This is a Transmit FIFO (0 = Rx FIFO)
#define AC97_FIFO_ST_DIR_TX          (1u <<  AC97_FIFO_ST_DIR_TX_SHF) 
                                    // SW supports DMA loop on this FIFO.
#define AC97_FIFO_ST_DMA_LP_ABLE    (1u <<  AC97_FIFO_ST_DMA_LP_ABLE_SHF ) 

                                    // DMA loop mode.
                                    // Special test mode for paired in / out 
                                    //  FIFOs.  No buffer reads or writes.
#define AC97_FIFO_ST_DMA_LP_MODE     (1u <<  AC97_FIFO_ST_DMA_LP_MODE_SHF )
                                    // Use interrupts for ACUNIT FIFO status
#define AC97_FIFO_ST_FIFO_ISR_MODE   (1u << AC97_FIFO_ST_FIFO_ISR_MODE_SHF ) 
                                    // Use interrupts for DMA events
#define AC97_FIFO_ST_DMA_ISR_MODE    (1u << AC97_FIFO_ST_DMA_ISR_MODE_SHF ) 

                                    // The FIFO's logical open state (1=open)
#define AC97_FIFO_ST_OPEN            (1u <<  AC97_FIFO_ST_OPEN_SHF )
                                    // Started and not fully stopped
#define AC97_FIFO_ST_ACTIVE          (1u << AC97_FIFO_ST_ACTIVE_SHF ) 
                                    // DMA is running.  Otherwise, stopped.
#define AC97_FIFO_ST_DMA_RUNNING     (1u <<  AC97_FIFO_ST_DMA_RUNNING_SHF ) 

                                    // FIFO status ISR registered with ACUNIT
#define AC97_FIFO_ST_FIFO_ISR_REG    (1u << AC97_FIFO_ST_FIFO_ISR_REG_SHF ) 
                                    // Acquired a DMA channel.  Value in
                                    //  dmaChannel member is valid.
#define AC97_FIFO_ST_DMA_CHAN_ACQ    (1u <<  AC97_FIFO_ST_DMA_CHAN_ACQ_SHF ) 
                                    // DMA events ISR registered for channel
#define AC97_FIFO_ST_DMA_ISR_REG     (1u << AC97_FIFO_ST_DMA_ISR_REG_SHF ) 

                                    // Underrun or overrun for target FIFO
                                    //  Data corrupted, no restart needed.
                                    //  ac97FifoErrs member is nonzero.
#define AC97_FIFO_ST_FIFO_ERR        (1u <<  AC97_FIFO_ST_FIFO_ERR_SHF )
                                    // DCSR_BUSERRINTR error on target DMA 
                                    //   channel.  Restart was needed, data
                                    //   corrupted.
#define AC97_FIFO_ST_DCSR_BUSERRINTR  (1u <<  AC97_FIFO_ST_DCSR_BUSERRINTR_SHF )

#define AC97_FIFO_ST_DCSR_STARTINTR   (1u <<  AC97_FIFO_ST_DCSR_STARTINTR_SHF )

#define AC97_FIFO_ST_DCSR_ENDINTR     (1u <<  AC97_FIFO_ST_DCSR_ENDINTR_SHF )

#define AC97_FIFO_ST_DCSR_STOPINTR    (1u <<  AC97_FIFO_ST_DCSR_STOPINTR_SHF )


                                    // XS DMA module reported that no DMA
                                    //  channel was available.
#define AC97_FIFO_ST_DMA_CHAN_NA     (1u <<  AC97_FIFO_ST_DMA_CHAN_NA_SHF )
                                    // Read on a Write Fifo or write on Read
                                    // Fifo.  Also, either on a closed Fifo.
                                    // Read or write in DMA Loop mode.
#define AC97_FIFO_ST_INVALID_OP      (1u <<  AC97_FIFO_ST_INVALID_OP_SHF )
                                    // Driver gave up after restarting DMA
                                    //  channel AC97_DMA_ERR_RESTARTS times
                                    // Operation aborted, need to close and
                                    //  reopen FIFO.
#define AC97_FIFO_ST_DMA_TOO_MANY    (1u <<  AC97_FIFO_ST_DMA_TOO_MANY_SHF ) 


typedef enum Ac97DmaBufModeE
{
    AC97_DMA_BUF_MODE_DOUBLE,
    AC97_DMA_BUF_MODE_GLITCH_RESIST
    
} Ac97DmaBufModeT;

                                    // Bitwise AND mask to clear event and 
                                    //  error indications from fifoStatus member
                                    // List only event and error indicators
#define AC97_FIFO_ST_CLR_EVNT_MSK  (~(AC97_FIFO_ST_FIFO_ERR         | \
                                      AC97_FIFO_ST_DCSR_BUSERRINTR  | \
                                      AC97_FIFO_ST_DMA_TOO_MANY     | \
                                      AC97_FIFO_ST_DMA_CHAN_NA      | \
                                      AC97_FIFO_ST_INVALID_OP        ))

                                    // Bitwise AND mask to clear out error
                                    // indications and otherwise initialize 
                                    // the fifoStatus member for opening.
                                    // Might have kept the DMA channel.
                                    // List all bits that shouldn't be touched.
#define AC97_FIFO_ST_OPEN_MSK      (AC97_FIFO_ST_DIR_TX           | \
                                    AC97_FIFO_ST_DMA_LP_ABLE      | \
                                    AC97_FIFO_ST_DMA_LP_MODE      | \
                                    AC97_FIFO_ST_DMA_CHAN_ACQ     | \
                                    AC97_FIFO_ST_FIFO_ISR_MODE    | \
                                    AC97_FIFO_ST_FIFO_ISR_REG     | \
                                    AC97_FIFO_ST_DMA_ISR_MODE       )

/*
*******************************************************************************
    Required services definitions:
*******************************************************************************
*/

// function typedefs for API structure

typedef struct  Ac97ContextS* Ac97ContextPT; // Need for dumb single-pass compiler.

typedef UINT32 (*Ac97GeneralHwControlFnPT) (Ac97ContextPT);

typedef UINT32 (*Ac97GetAnyMixerRegisterFnPT) (Ac97ContextPT, AC97MixerRegisterIdT, PUINT16);
typedef UINT32 (*Ac97SetAnyMixerRegisterFnPT) (Ac97ContextPT, AC97MixerRegisterIdT, UINT16);

typedef UINT32 (*Ac97GetStereoSideValueFnPT) (Ac97ContextPT, PUINT8);
typedef UINT32 (*Ac97SetStereoSideValueFnPT) (Ac97ContextPT, UINT8 );

typedef UINT32 (*Ac97GetEnableFnPT) (Ac97ContextPT, BOOL*);
typedef UINT32 (*Ac97SetEnableFnPT) (Ac97ContextPT, BOOL );

typedef UINT32 (*Ac97GetWholeRegFnPT) (Ac97ContextPT, PUINT16);
typedef UINT32 (*Ac97SetWholeRegFnPT) (Ac97ContextPT, UINT16 );

typedef UINT32 (*Ac97GetVendorIDandRevFnPT) (Ac97ContextPT, PCHAR, PINT);


////////////////////////////////////////////////////////////////////////////////////////

    // Comprises a set of pointers to functions for the API services.
    // This is a union of the APIs of all supported AC'97 codecs.  Not all are 
    //  valid at any one time; the default
    // It is organized principally by the AC'97 codec mixer registers that
    //  mediate most of the services.

typedef struct  Ac97ServicesT       
{

    int makeTheCompilerHappy;

    #if 0

    /************************  Original AC97 mixer registers *****************/

    // Universal access: "back door"
    Ac97GetAnyMixerRegisterFnPT ac97GetAnyMixerRegisterFnP;
    Ac97SetAnyMixerRegisterFnPT ac97SetAnyMixerRegisterFnP;

    // 0x00
    Ac97GeneralHwControlFnPT ac97ResetRegistersAllFnP; 

    Ac97GetWholeRegFnPT ac97GetCapabilitiesFnP;

//    #define AC97_MAX_CAPABILITIES
//    UINT32 Ac97DecodeCapabilities (unsigned int capabilitiesList, );

    // 0x02
    Ac97GetStereoSideValueFnPT Ac97GetMasterVolLeftFnP; 
    Ac97GetStereoSideValueFnPT Ac97GetMasterVolRightFnP;
    Ac97GetEnableFnPT          Ac97GetMasterVolMuteFnP; 

    Ac97SetStereoSideValueFnPT Ac97SetMasterVolLeftFnP; 
    Ac97SetStereoSideValueFnPT Ac97SetMasterVolRightFnP;
    Ac97SetEnableFnPT          Ac97SetMasterVolMuteFnP; 

    // 0x04
// lower priority       ac97GetHeadphoneVol...FnP;
// lower priority       ac97SetHeadphoneVol...FnP;

    // 0x06
// lower priority       ac97GetMasterVolMono...FnP;