registerequ.h

pxa270 NOR FLASH驱动代码

#define DRCMR30     0x40000178      //Request to Channel Map Register for USB endpoint 6 request
#define DRCMR31     0x4000017C      //Request to Channel Map Register for USB endpoint 7 request
#define DRCMR32     0x40000180      //Request to Channel Map Register for USB endpoint 8 request
#define DRCMR33     0x40000184      //Request to Channel Map Register for USB endpoint 9 request
#define DRCMR34     0x40000188      //Reserved
#define DRCMR35     0x4000018C      //Request to Channel Map Register for USB endpoint 11 request
#define DRCMR36     0x40000190      //Request to Channel Map Register for USB endpoint 12 request
#define DRCMR37     0x40000194      //Request to Channel Map Register for USB endpoint 13 request
#define DRCMR38     0x40000198      //Request to Channel Map Register for USB endpoint 14 request
#define DRCMR39     0x4000019C      //Reserved
#define DDADR0      0x40000200      //DMA Descriptor Address register channel 0
#define DSADR0      0x40000204      //DMA Source Address register channel 0
#define DTADR0      0x40000208      //DMA Target address register channel 0
#define DCMD0       0x4000020C      //DMA command address register channel 0
#define DDADR1      0x40000210      //DMA Descriptor Address register channel 1
#define DSADR1      0x40000214      //DMA Source Address register channel 1
#define DTADR1      0x40000218      //DMA Target address register channel 1
#define DCMD1       0x4000021C      //DMA command address register channel 1
#define DDADR2      0x40000220      //DMA Descriptor Address register channel 2
#define DSADR2      0x40000224      //DMA Source Address register channel 2
#define DTADR2      0x40000228      //DMA Target address register channel 2
#define DCMD2       0x4000022C      //DMA command address register channel 2
#define DDADR3      0x40000230      //DMA Descriptor Address register channel 3
#define DSADR3      0x40000234      //DMA Source Address register channel 3
#define DTADR3      0x40000238      //DMA Target address register channel 3
#define DCMD3       0x4000023C      //DMA command address register channel 3
#define DDADR4      0x40000240      //DMA Descriptor Address register channel 4
#define DSADR4      0x40000244      //DMA Source Address register channel 4
#define DTADR4      0x40000248      //DMA Target address register channel 4
#define DCMD4       0x4000024C      //DMA command address register channel 4
#define DDADR5      0x40000250      //DMA Descriptor Address register channel 5
#define DSADR5      0x40000254      //DMA Source Address register channel 5
#define DTADR5      0x40000258      //DMA Target address register channel 5
#define DCMD5       0x4000025C      //DMA command address register channel 5
#define DDADR6      0x40000260      //DMA Descriptor Address register channel 6
#define DSADR6      0x40000264      //DMA Source Address register channel 6
#define DTADR6      0x40000268      //DMA Target address register channel 6
#define DCMD6       0x4000026C      //DMA command address register channel 6
#define DDADR7      0x40000270      //DMA Descriptor Address register channel 7
#define DSADR7      0x40000274      //DMA Source Address register channel 7
#define DTADR7      0x40000278      //DMA Target address register channel 7
#define DCMD7       0x4000027C      //DMA command address register channel 7
#define DDADR8      0x40000280      //DMA Descriptor Address register channel 8
#define DSADR8      0x40000284      //DMA Source Address register channel 8
#define DTADR8      0x40000288      //DMA Target address register channel 8
#define DCMD8       0x4000028C      //DMA command address register channel 8
#define DDADR9      0x40000290      //DMA Descriptor Address register channel 9
#define DSADR9      0x40000294      //DMA Source Address register channel 9
#define DTADR9      0x40000298      //DMA Target address register channel 9
#define DCMD9       0x4000029C      //DMA command address register channel 9
#define DDADR10     0x400002A0      //DMA Descriptor Address register channel 10
#define DSADR10     0x400002A4      //DMA Source Address register channel 10
#define DTADR10     0x400002A8      //DMA Target address register channel 10
#define DCMD10      0x400002AC      //DMA command address register channel 10
#define DDADR11     0x400002B0      //DMA Descriptor Address register channel 11
#define DSADR11     0x400002B4      //DMA Source Address register channel 11
#define DTADR11     0x400002B8      //DMA Target address register channel 11
#define DCMD11      0x400002BC      //DMA command address register channel 11
#define DDADR12     0x400002C0      //DMA Descriptor Address register channel 12
#define DSADR12     0x400002C4      //DMA Source Address register channel 12
#define DTADR12     0x400002C8      //DMA Target address register channel 12
#define DCMD12      0x400002CC      //DMA command address register channel 12
#define DDADR13     0x400002D0      //DMA Descriptor Address register channel 13
#define DSADR13     0x400002D4      //DMA Source Address register channel 13
#define DTADR13     0x400002D8      //DMA Target address register channel 13
#define DCMD13      0x400002DC      //DMA command address register channel 13
#define DDADR14     0x400002E0      //DMA Descriptor Address register channel 14
#define DSADR14     0x400002E4      //DMA Source Address register channel 14
#define DTADR14     0x400002E8      //DMA Target address register channel 14
#define DCMD14      0x400002EC      //DMA command address register channel 14
#define DDADR15     0x400002F0      //DMA Descriptor Address register channel 15
#define DSADR15     0x400002F4      //DMA Source Address register channel 15
#define DTADR15     0x400002F8      //DMA Target address register channel 15
#define DCMD15      0x400002FC      //DMA command address register channel 15

/*LCD Controller register Locations */
/*------------------------------------------------------------*/
#define LCCR0       0x44000000      //LCD controller control register 0
#define LCCR1       0x44000004      //LCD controller control register 1
#define LCCR2       0x44000008      //LCD controller control register 2
#define LCCR3       0x4400000C      //LCD controller control register 3
#define FBR0        0x44000020      //DMA channel 0 frame branch register
#define FBR1        0x44000024      //DMA channel 1 frame branch register
#define LCSR        0x44000038      //LCD controller status register
#define LIIDR       0x4400003C      //LCD controller interrupt ID register
#define TRGBR       0x44000040      //TMED RGB seed register
#define TCR         0x44000044      //TMED control register
#define FDADR0      0x44000200      //DMA channel 0 frame descriptor address register
#define FSADR0      0x44000204      //DMA channel 0 frame source address register
#define FIDR0       0x44000208      //DMA channel 0 frame ID register
#define LDCMD0      0x4400020C      //DMA channel 0 command register
#define FDADR1      0x44000210      //DMA channel 1 frame descriptor address register 
#define FSADR1      0x44000214      //DMA channel 1 frame source address register
#define FIDR1       0x44000218      //DMA channel 1 frame ID register
#define LDCMD1      0x4400021C      //DMA channel 1 command register

/*Analog to Digital Converter register locations*/
/*------------------------------------------------------------*/
#define ADCD        0x41200000      //ADC Data register
#define ADCS        0x41200004      //ADC control register
#define ADCE        0x41200008      //ADC enable register
#define ADCTSC      0x4120000C      //ADC touch screen control register
#define ADCTSS1     0x41200010      //ADC touch screen setup register 1
#define ADCTSS2     0x41200014      //ADC touch screen setup register 2

/*SSP register locations*/
/*------------------------------------------------------------*/
#define SSCR0       0x41000000      //SSP control register 0
#define SSCR1       0x41000004      //SSP control register 1
#define SSSR        0x41000008      //SSP status register 
#define SSITR       0x4100000C      //SSP interrupt test register
#define SSDR        0x41000010      //SSP data read/write register

/*I2C register locations */
/*------------------------------------------------------------*/
#define IBMR            0x40301680      //I2C bus monitor register
#define IDBR            0x40301688      //I2C data buffer register
#define ICR             0x40301690      //I2C control register
#define ISR             0x40301698      //I2C status register
#define ISAR            0x403016A0      //I2C slave address register
#define I2CCR           0x403016A8      //I2C clock count register

/*----- UART Registers Address Locations-----*/
/*---------------------------------------------*/

#define wTHR_BT     0x40200000      //DLAB = 0  WO  8bit - Transmit Holding Register
#define wRBR_BT     0x40200000      //DLAB = 0  RO  8bit - Recieve Buffer Register
#define wDLL_BT     0x40200000      //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define wIER_BT     0x40200004      //DLAB = 0  RW  8bit - Interrupt Enable Register
#define wDLH_BT     0x40200004      //DLAB = 1  RW  8bit - Divisor Latch High Register
#define wIIR_BT     0x40200008      //DLAB = X  RO  8bit - Interrupt Identification Register
#define wFCR_BT     0x40200008      //DLAB = X  WO  8bit - FIFO Control Register
#define wLCR_BT     0x4020000C      //DLAB = X  RW  8bit - Line Control Register
#define wMCR_BT     0x40200010      //DLAB = X  RW  8bit - Modem Control Regiser
#define wLSR_BT     0x40200014      //DLAB = X  RO  8bit - Line Status Register
#define wMSR_BT     0x40200018      //DLAB = X  RO  8bit - Modem Status Register
#define wSCR_BT     0x4020001C      //DLAB = X  RW  8bit - Scratchpad Register
#define wIRDASEL_BT 0x40200020      //DLAB = X  RW  8bit - IrDA Select Register

#define wTHR_FF     0x40100000      //DLAB = 0  WO  8bit - Transmit Holding Register
#define wRBR_FF     0x40100000      //DLAB = 0  RO  8bit - Recieve Buffer Register
#define wDLL_FF     0x40100000      //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define wIER_FF     0x40100004      //DLAB = 0  RW  8bit - Interrupt Enable Register
#define wDLH_FF     0x40100004      //DLAB = 1  RW  8bit - Divisor Latch High Register
#define wIIR_FF     0x40100008      //DLAB = X  RO  8bit - Interrupt Identification Register
#define wFCR_FF     0x40100008      //DLAB = X  WO  8bit - FIFO Control Register
#define wLCR_FF     0x4010000C      //DLAB = X  RW  8bit - Line Control Register
#define wMCR_FF     0x40100010      //DLAB = X  RW  8bit - Modem Control Regiser
#define wLSR_FF     0x40100014      //DLAB = X  RO  8bit - Line Status Register
#define wMSR_FF     0x40100018      //DLAB = X  RO  8bit - Modem Status Register
#define wSCR_FF     0x4010001C      //DLAB = X  RW  8bit - Scratchpad Register
#define wIRDASEL_FF 0x40100020      //DLAB = X  RW  8bit - IrDA Select Register

#define wTHR_ST     0x40700000      //DLAB = 0  WO  8bit - Transmit Holding Register
#define wRBR_ST     0x40700000      //DLAB = 0  RO  8bit - Recieve Buffer Register
#define wDLL_ST     0x40700000      //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define wIER_ST     0x40700004      //DLAB = 0  RW  8bit - Interrupt Enable Register
#define wDLH_ST     0x40700004      //DLAB = 1  RW  8bit - Divisor Latch High Register
#define wIIR_ST     0x40700008      //DLAB = X  RO  8bit - Interrupt Identification Register
#define wFCR_ST     0x40700008      //DLAB = X  WO  8bit - FIFO Control Register
#define wLCR_ST     0x4070000C      //DLAB = X  RW  8bit - Line Control Register
#define wMCR_ST     0x40700010      //DLAB = X  RW  8bit - Modem Control Regiser
#define wLSR_ST     0x40700014      //DLAB = X  RO  8bit - Line Status Register
#define wMSR_ST     0x40700018      //Reserved
#define wSCR_ST     0x4070001C      //DLAB = X  RW  8bit - Scratchpad Register
#define wIRDASEL_ST 0x40700020      //DLAB = X  RW  8bit - IrDA Select Register

#define BT_TBE      4
#define FF_TBE      5
#define ST_TBE      6

/*Infrared Communication Port */
/*------------------------------------------------------------*/
#define ICCR0       0x40800000      //ICP control register 0
#define ICCR1       0x40800004      //ICP control register 1
#define ICCR2       0x40800008      //ICP control register 2
#define ICDR        0x4080000C      //ICP data register
#define ICSR0       0x40800014      //ICP status register 0
#define ICSR1       0x40800018      //ICP status register 1

/*AC97 register locations---------these are speculated addresses and should be double checked upon testing*/
/*------------------------------------------------------------*/
#define POCR        0x40500000      //PCM out control register
#define PICR        0x40500004      //PCM in control register
#define MCCR        0x40500008      //Mic in control register
#define GCR         0x4050000C      //Global Control Register
#define POSR        0x40500010      //PCM out status register
#define PISR        0x40500014      //PCM in status register
#define MCSR        0x40500018      //Mic in status register
#define GSR         0x4050001C      //global status register
#define CAR         0x40500020      //CODEC access register
#define PCDR        0x40500040      //audio fifo data register
#define MCDR        0x40500060      //mic in fifo data register
#define MOCR        0x40500100      //Modem out control register
#define MICR        0x40500108      //Modem in control register
#define MOSR        0x40500110      //Modem out status register
#define MISR        0x40500118      //modem in status register
#define MODR        0x40500140      //Modem fifo data register

/*I2S register locations*/
/*------------------------------------------------------------*/
#define SACR0       0x40400000      //Global control register
#define SACR1       0x40400004      //Serial Audio I2S/MSB justified control register
#define SASR0       0x4040000C      //Serial audio I2S/MSB justified interface and fifo status register
#define SAIMR       0x40400014      //Serial audio intrerupt mask register
#define SAICR       0x40400018      //Serial audio interrupt clear register
#define SAITR       0x4040005C      //Serial audio interrupt test register
#define SADIV       0x40400060      //Audio clock divider register
#define SADR        0x40400080      //Serial audio data register

#endif