📄 registerequ.h
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#ifndef __REGISTEREQU_H__
#define __REGISTEREQU_H__
/* GPIO Register locations */
/*------------------------------------------------------------*/
#define GPLR_x 0x40E00000 //GPIO pin-level register 31:0
#define GPLR_y 0x40E00004 //GPIO pin-level register 63:32
#define GPLR_z 0x40E00008 //GPIO pin-level register 80:64
#define GPDR_x 0x40E0000C //GPIO pin-direction register 31:0
#define GPDR_y 0x40E00010 //GPIO pin-direction register 63:32
#define GPDR_z 0x40E00014 //GPIO pin-direction register 80:64
#define GPSR_x 0x40E00018 //GPIO pin output set register 31:0
#define GPSR_y 0x40E0001C //GPIO pin output set register 63:32
#define GPSR_z 0x40E00020 //GPIO pin output set register 80:64
#define GPCR_x 0x40E00024 //GPIO pin output clear register 31:0
#define GPCR_y 0x40E00028 //GPIO pin output clear register 63:32
#define GPCR_z 0x40E0002C //GPIO pin output clear register 80:64
#define GRER_x 0x40E00030 //GPIO rising edge detect register 31:0
#define GRER_y 0x40E00034 //GPIO rising edge detect register 63:32
#define GRER_z 0x40E00038 //GPIO rising edge detect register 80:64
#define GFER_x 0x40E0003C //GPIO falling edge detect register 31:0
#define GFER_y 0x40E00040 //GPIO falling edge detect register 63:32
#define GFER_z 0x40E00044 //GPIO falling edge detect register 80:64
#define GEDR_x 0x40E00048 //GPIO edge detect status register 31:0
#define GEDR_y 0x40E0004C //GPIO edge detect status register 63:32
#define GEDR_z 0x40E00050 //GPIO edge detect status register 80:64
#define GAFR0_x 0x40E00054 //GPIO alternate funciton select register 15:0
#define GAFR1_x 0x40E00058 //GPIO alternate function select register 31:16
#define GAFR0_y 0x40E0005C //GPIO alternate function select register 47:32
#define GAFR1_y 0x40E00060 //GPIO alternate function select register 63:48
#define GAFR0_z 0x40E00064 //GPIO alternate function select register 79:64
#define GAFR1_z 0x40E00068 //GPIO alternate function select register 80
// These register addresses are not defined yet
#define SVCR0 0x0
#define SVCR1 0x2
#define SVCR2 0x4
#define SVCR3 0x6
#define SVCR4 0x8
#define SVCR5 0xA
#define SVCR6 0xC
#define SVCR7 0xE
#define SVCR8 0x20
#define SVCR9 0x22
#define SVCR10 0x24
#define SVCR11 0x26
#define SVCR12 0x28
#define SVCR13 0x2A
#define SVCR14 0x2C
#define SVCR15 0x2E
#define SVCR16 0x30
#define SVDR0 0x32
#define SVDR1 0x34
#define SVDR2 0x36
#define SVDR3 0x38
#define SVDR4 0x3A
#define SVDR5 0x3C
#define SVPCR 0x3E
#define SVPDR_LO 0x40
#define SVPDR_HI 0x42
#define SVPWR_LO 0x44
#define SVPWR_HI 0x46
#define SVPPR_LO 0x48
#define SVPPR_HI 0x4A
#define SVPER 0x4C
#define SVPSR 0x4E
/*Interrupt Controller Register Locations */
/*------------------------------------------------------------*/
#define ICIP 0x40D00000 //Interrupt controller IRQ pending register
#define ICMR 0x40D00004 //Interrupt controller mask register
#define ICLR 0x40D00008 //Interrupt controller level register
#define ICFP 0x40D0000C //Interrupt controller FIQ pending register
#define ICPR 0x40D00010 //Interrupt controller pending register
#define ICCR 0x40D00014 //Interrupt controller control register
/* Real-Time Clock Register Locations */
/*------------------------------------------------------------*/
#define RCNR 0x40900000 //RTC count register
#define RTAR 0x40900004 //RTC alarm register
#define RTSR 0x40900008 //RTC status register
#define RTTR 0x4090000C //RTC timer trim register
/*OS Timer Register Locations */
/*------------------------------------------------------------*/
#define OSMR_0 0x40A00000 //OS timer match register 0
#define OSMR_1 0x40A00004 //OS timer match register 1
#define OSMR_2 0x40A00008 //OS timer match register 2
#define OSMR_3 0x40A0000C //OS timer match register 3
#define OSCR 0x40A00010 //OS timer counter register
#define OSSR 0x40A00014 //OS timer status register
#define OWER 0x40A00018 //OS timer watchdog enable register
#define OIER 0x40A0001C //OS timer interrupt enable register
/*Power Manager Register Locations */
/*------------------------------------------------------------*/
#define PMCR 0x40F00000 //Power manager control register
#define PSSR 0x40F00004 //Power manager sleep status register
#define PSPR 0x40F00008 //Power manager scratch pad register
#define PWER 0x40F0000C //Power manager wake-up enable register
#define PRER 0x40F00010 //Power manager GPIO rising edge detect enable register
#define PFER 0x40F00014 //Power manager GPIO falling edge detect enable register
#define PEDR 0x40F00018 //Power manager GPIO edge detect status register
#define PCFR 0x40F0001C //Power manager general configuration register
#define PGSR_x 0x40F00020 //Power manager GPIO sleep state register for GPIO 31:0
#define PGSR_y 0x40F00024 //Power manager GPIO sleep state register for GPIO 63:32
#define PGSR_z 0x40F00028 //Power manager GPIO sleep state register for GPIO 80:64
/*Reset Controller Register Location */
/*------------------------------------------------------------*/
#define RCSR 0x40F00030 //Reset controller status register
/*Clocks Manager register locations */
/*------------------------------------------------------------*/
#define CCCR 0x41300000 //Core Clock Configuration Register
#define CKEN 0x41300004 //Clock Enable Register
#define OSCC 0x41300008 //Oscillator Configuration Register
/* Pulse Width Modulator Register Locations */
/*------------------------------------------------------------*/
#define PWCR0 0x40B00000 //PWM Control Register 0
#define PWDR0 0x40B00004 //PWM Duty Cycle Register 0
#define PWPR0 0x40B00008 //PWM Period Control Register 0
#define PWCR1 0x40C00000 //PWM Control Register 1
#define PWDR1 0x40C00004 //PWM Duty Cycle Register 1
#define PWPR1 0x40C00008 //PWM Period Control Register 1
// These registers are not defined yet
#define PWCSR0 0x0
#define PWHTR0_HI 0x2
#define PWHTR0_LO 0x4
#define PWLTR0_HI 0x6
#define PWLTR0_LO 0x8
#define PWCSR1 0xA
#define PWHTR1_HI 0xC
#define PWHTR1_LO 0xE
#define PWLTR1_HI 0x10
#define PWLTR1_LO 0x12
/* Memory Interface Control Registers */
/*------------------------------------------------------------*/
#define MDFNFG 0x48000000 //SDRAM configuration register 0
#define MDREFR 0x48000004 //SDRAM refresh control register
#define MSC0 0x48000008 //Static memory control register 0
#define MSC1 0x4800000C //Static memory control register 1
#define MSC2 0x48000010 //Static memory control register 2
#define MECR 0x48000014 //Expansion memory bus configuration register
#define SXLCR 0x48000018 //LCR Value to be written to SDRAM-Timeing Synchronous Flash
#define SXCNFG 0x4800001C //Synchronous static memory control register
#define FLYCNFG 0x48000020 //Fly by DMA DVAL assert and deassert times
#define SXMRS 0x48000024 //MRS value to be written to synchronous Flash or SMROM
#define MCMEM0 0x48000028 //Card interface Common Memory Space Socket 0 Timing Configuration
#define MCMEM1 0x4800002C //Card interface Common Memory Space Socket 1 Timing Configuration
#define MCATT0 0x48000030 //Card interface Atriibute Space Socket 0 timing configuration
#define MCATT1 0x48000034 //Card interface Attribute Space Socket 1 Timing configuration
#define MCIO0 0x48000038 //Card interface I/O Space Socket 0 Timing Configuration
#define MCIO1 0x4800003C //Card interface I/O Space Socket 1 Timing configuration
#define MDMRS 0x48000040 //MRS value to be written to SDRAM
#define BOOT_DEF 0x48000044 //Read-Only Boot-time register
/* DMAC Controller Registers */
/*------------------------------------------------------------*/
#define DCSR0 0x40000000 //DMA Control/Status Register for Channel 0
#define DCSR1 0x40000004 //DMA Control/Status Register for Channel 1
#define DCSR2 0x40000008 //DMA Control/Status Register for Channel 2
#define DCSR3 0x4000000C //DMA Control/Status Register for Channel 3
#define DCSR4 0x40000010 //DMA Control/Status Register for Channel 4
#define DCSR5 0x40000014 //DMA Control/Status Register for Channel 5
#define DCSR6 0x40000018 //DMA Control/Status Register for Channel 6
#define DCSR7 0x4000001C //DMA Control/Status Register for Channel 7
#define DCSR8 0x40000020 //DMA Control/Status Register for Channel 8
#define DCSR9 0x40000024 //DMA Control/Status Register for Channel 9
#define DCSR10 0x40000028 //DMA Control/Status Register for Channel 10
#define DCSR11 0x4000002C //DMA Control/Status Register for Channel 11
#define DCSR12 0x40000030 //DMA Control/Status Register for Channel 12
#define DCSR13 0x40000034 //DMA Control/Status Register for Channel 13
#define DCSR14 0x40000038 //DMA Control/Status Register for Channel 14
#define DCSR15 0x4000003C //DMA Control/Status Register for Channel 15
#define DINT 0x400000F0 //DMA interrupt Register
#define DRCMR0 0x40000100 //Request to Channel Map Register for DREQ 0
#define DRCMR1 0x40000104 //Request to Channel Map Register for DREQ 1
#define DRCMR2 0x40000108 //Request to Channel Map Register for I2S receive Request
#define DRCMR3 0x4000010C //Request to Channel Map Register for I2S transmit Request
#define DRCMR4 0x40000110 //Request to Channel Map Register for BTUART receive request
#define DRCMR5 0x40000114 //Request to Channel Map Register for BTUART transmit request
#define DRCMR6 0x40000118 //Request to Channel Map Register for FFUART receive request
#define DRCMR7 0x4000011C //Request to Channel Map Register for FFUART transmit request
#define DRCMR8 0x40000120 //Request to Channel Map Register for AC97 microphone request
#define DRCMR9 0x40000124 //Request to Channel Map Register for AC97 modem recieve request
#define DRCMR10 0x40000128 //Request to Channel Map Register for AC97 modem transmit request
#define DRCMR11 0x4000012C //Request to Channel Map Register for AC97 audio receive request
#define DRCMR12 0x40000130 //Request to Channel Map Register for AC97 audio transmit request
#define DRCMR13 0x40000134 //Request to Channel Map Register for SSP receive request
#define DRCMR14 0x40000138 //Request to Channel Map Register for SSP transmit request
#define DRCMR15 0x4000013C //Reserved
#define DRCMR16 0x40000140 //Reserved
#define DRCMR17 0x40000144 //Request to Channel Map Register for ICP receive request
#define DRCMR18 0x40000148 //Request to Channel Map Register for ICP transmit request
#define DRCMR19 0x4000014C //Request to Channel Map Register for STUART receive request
#define DRCMR20 0x40000150 //Request to Channel Map Register for STUART transmit request
#define DRCMR21 0x40000154 //Request to Channel Map Register for MMC receive request
#define DRCMR22 0x40000158 //Request to Channel Map Register for MMC transmit request
#define DRCMR23 0x4000015C //Reserved
#define DRCMR24 0x40000160 //Reserved
#define DRCMR25 0x40000164 //Request to Channel Map Register for USB endpoint 1 request
#define DRCMR26 0x40000168 //Request to Channel Map Register for USB endpoint 2 request
#define DRCMR27 0x4000016C //Request to Channel Map Register for USB endpoint 3 request
#define DRCMR28 0x40000170 //Request to Channel Map Register for USB endpoint 4 request
#define DRCMR29 0x40000174 //Reserved
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