cotulla.h

pxa270 NOR FLASH驱动代码

/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       cotulla.h
**
**  PURPOSE:        <Module description here>
**
**  LAST MODIFIED:  01/12/2001
******************************************************************************/
#ifndef _cotulla_h
#define _cotulla_h

/*
*******************************************************************************
*
*    Functional Proto-types
*
*******************************************************************************
*/
void PauseInMsecs(unsigned blink);
void KXsGetClockRate(PVOID, PCHAR);
/*
*******************************************************************************
*    CPSR Definitions
*******************************************************************************
*/
#define CPSR_Mode_USR (0x10U << 0)
#define CPSR_Mode_FIQ (0x11U << 0)
#define CPSR_Mode_IRQ (0x12U << 0)
#define CPSR_Mode_SVC (0x13U << 0)
#define CPSR_Mode_ABT (0x17U << 0)
#define CPSR_Mode_UND (0x1BU << 0)
#define CPSR_Mode_SYS (0x1FU << 0)
#define CPSR_T_Bit    (0x1U  << 5)
#define CPSR_F_Bit    (0x1U  << 6)
#define CPSR_I_Bit    (0x1U  << 7)
#define CPSR_Q_Bit    (0x1U  << 27)
#define CPSR_V_Bit    (0x1U  << 28)
#define CPSR_C_Bit    (0x1U  << 29)
#define CPSR_Z_Bit    (0x1U  << 30)
#define CPSR_N_Bit    (0x1U  << 31)

// Two constants for PhysicalToVirtual second parameter
#define XS_PTV_GET_UNCACHED  0
#define XS_PTV_GET_CACHED    1

// Processor ID definitions in the form:
// Bits 31:24 - Implementation Trademark - 0x69 - Intel(r) Corporation
//      23:16 - Architecture Version - 0x05 - ARM V5
//      15:13 - Core Generation - 0b001 - Intel(r) XScale(tm) Core 1st generation
//                                0b010 - Intel(r) XScale(tm) Core 2nd generation
//      12:10 - Core Revision - 0b000 - Revision 1 for Bulverde A0/A1
//       9:4  - Product Number - 0b010000 - PXA2xx Application Processor
//                               0b010001 - Bulverde Application Processor
//       3:0  - Product Revision - 0b0000 - A0 Stepping
//                                 0b0001 - A1 Stepping
//
//                   33222222 22221111 111 111 000000 0000
//                   10987654 32109876 543 210 987654 3210
//                   -------- -------- --- --- ------ ----
// 0x69054110 - A0 - 01101001 00000101 010 000 010001 0000 - Bulverde A0
// 0x69054111 - A1 - 01101001 00000101 010 000 010001 0001 - Bulverde A1
//

// Processor ID definitions.
#define CPU_TRADEMARK_MASK     (0xFFU << 24)    // 0x69 - Intel(r) Corporation
#define CPU_ARCH_VER_MASK      (0xFFU << 16)    // 0x05 - ARM V5
#define CPU_CORE_GEN_MASK      (0x07U << 13)    // 0x2 - Intel XScale 2nd generation
#define CPU_CORE_REV_MASK      (0x07U << 10)    // 0x0 - Revision 1 for A0/A1
#define CPU_PRODUCT_NUM_MASK   (0x3FU << 4)     // 0x11 - Bulverde
#define CPU_PRODUCT_REV_MASK   (0x0FU << 0)     // 0x1 - Step A1

// Processor ID macros
#define CPU_TRADEMARK(x)   ((x & CPU_TRADEMARK_MASK)   >> 24)
#define CPU_ARCH_VER(x)    ((x & CPU_ARCH_VER_MASK)    >> 16)
#define CPU_CORE_GEN(x)    ((x & CPU_CORE_GEN_MASK)    >> 13)
#define CPU_CORE_REV(x)    ((x & CPU_CORE_REV_MASK)    >> 10)
#define CPU_PRODUCT_NUM(x) ((x & CPU_PRODUCT_NUM_MASK) >> 4)
#define CPU_PRODUCT_REV(x) ((x & CPU_PRODUCT_REV_MASK) >> 0)

// Stepping definitions.
#define STEP_A0    0x00
#define STEP_A1    0x01
#define STEP_B0    0x02
#define STEP_B1    0x03
#define STEP_C0    0x04
#define STEP_C2    0x05
#define STEP_C3    0x06
#define STEP_C4    0x07

typedef enum ClockFreqTypeE
{
    CORE_FREQ,
    SYS_BUS_FREQ,
    MEM_BUS_FREQ,
    MEM_CLOCK_FREQ,
    LCD_CLOCK_FREQ
} ClockFreqTypeT;

// Clocks freq. structure
typedef struct ClockFreqStringsTableS {
    PCHAR  coreFreq;
    PCHAR  sysBusFreq;
    PCHAR  memBusFreq;
    PCHAR  memClockFreq;
} ClockFreqStringsTableT;

typedef struct ClockFreqValueTableS {
	UINT32	selectionValue;
	UINT32	coreFreq;
	UINT32  turboFreq;
} ClockFreqValueTableT;

typedef struct ProcessorRegistersS
{
    UINT32 r0;
    UINT32 r1;
    UINT32 r2;
    UINT32 r3;
    UINT32 r4;
    UINT32 r5;
    UINT32 r6;
    UINT32 r7;
    UINT32 r8;
    UINT32 r9;
    UINT32 r10;
    UINT32 r11;
    UINT32 r12;
    UINT32 r13;
    UINT32 r14;
    UINT32 r15;
    UINT32 cpsr;
} ProcessorRegistersT;

/*
*******************************************************************************
*   Prototypes Declaration
*******************************************************************************
*/

// Assembly Language prototypes
UINT VirtualToPhysical(PVOID vaP, PUINT32 paP);
UINT xlli_getFreq(VOID);
UINT PhysicalToVirtual(UINT32 pa, UINT getCachedMem, PVOID* vaPP);
UINT GetCpuVersion(VOID);
UINT IsMMUEnabled(VOID);
UINT IsICacheEnabled(VOID);
UINT IsDCacheEnabled(VOID);


/*
*******************************************************************************
    Function prototypes
*******************************************************************************
*/
PCHAR XsGetCpuTrademark(VOID);
PCHAR XsGetCpuArchitecture(VOID);
PCHAR XsGetCpuCoreGeneration(VOID);
PCHAR XsGetCpuCoreRevision(VOID);
PCHAR XsGetCpuProductNumber(BOOL flag);
PCHAR XsGetCpuProductRevision(BOOL flag);
PCHAR XsGetMMUConfiguration(VOID);

VOID XsSetClockRate (int clkVal);
INT XsGetClockRate (VOID);
PVOID SA_NonCacheableAddress (void *p);
VOID SA_SelectAlternateFunction (unsigned mask);
VOID SA_RestoreAlternateFunction (unsigned mask);
VOID SA_SelectAlternatePin (int func);
VOID SA_MapPage (void *pa, void *va, int ap, int dom, int c, int b);
VOID SA_MapSmallPage (void *pa, void *va, int ap, int dom, int c, int b);
VOID SA_SelectAlternateClock (int clock);
VOID XsMainSWInit (void);
UINT32 XsMainHWSetup(VOID);
VOID XsGetClockRateString (VOID);
PCHAR XsCpuTypeString (void);
VOID SA_SetupInterruptVector (int fiq);

#endif /* _cotulla_h_ */