📄 main.s
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; here because we are jumping back to the same address, just executing from
; RAM. At this point we are running from ROM that has been remapped to ROM_BASE.
;
; WARNING: Don't add any instruction between the label StartAtRAM
; and the SUB instructions below. This code is attempting to calculate
; the delta offset of this routine to cover the case when DM is stored
; in high flash.
;
StartAtRAM
sub r0, pc, #8 ; Get the current program counter
ldr r1, =ROM_BASE ; Get the beginning of flash
sub r0, r0, r1 ; Calculate the current offset
ldr r1, =StartAtRAM ; Get the compile time offset
sub r2, r0, r1 ; Calculate the program offset
;
; Calculate the new address in RAM by taking the current address and subtract
; ROM_BASE. On return, we should be running from RAM.
;
ldr r0, =ROM_BASE ; Get Destination Address
add r0, r0, r2 ; Take into account our program offset
sub pc,lr,r0 ; Back plus our load offset
;------------------------------------------------------------------------------
;
; FUNCTION:
; VirtualToPhysical
;
; DESCRIPTION:
; This routine will return the physical address of the specified virtual
; address.
;
; INPUT PARAMETERS:
; r0 - Virtual address of interest
; r1 - Address of variable to hold resultant physical address
;
; RETURNS:
; r0 - 0 = Success, -1 = Failure
; [r1] - Physical address of the specified virtual address
;
; GLOBAL EFFECTS:
; None
;
; ASSUMPTIONS:
; None
;
; CALLS:
; None
;
; CALLED BY:
; This routine can be called by "C" code.
;
; PROTOTYPE:
; UINT VirtualToPhysical(PVOID VA, PVOID PA);
;
;------------------------------------------------------------------------------
VirtualToPhysical
stmfd sp!, {r2 - r5, lr} ; Save registers
VirtToPhys v_cbSDRAM,s_cbSDRAM,p_cbSDRAM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F390 ; If zero, exit
VirtToPhys i_xxSDRAM,s_xxSDRAM,i_xxSDRAM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F390 ; If zero, exit
VirtToPhys v_cxSDRAM,s_cxSDRAM,p_cxSDRAM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F390 ; If zero, exit
VirtToPhys i_xxPCMCIA,s_xxPCMCIA,i_xxPCMCIA,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F390 ; If zero, exit
VirtToPhys i_xxProcessorReg,s_xxProcessorReg,i_xxProcessorReg,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F390 ; If zero, exit
VirtToPhys i_xxPlatformReg,s_xxPlatformReg,i_xxPlatformReg,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F390 ; If zero, exit
VirtToPhys v_xxBOOTROM,s_xxBOOTROM,p_xxBOOTROM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F390 ; If zero, exit
VirtToPhys v_xxALTROM,s_xxALTROM,p_xxALTROM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F390 ; If zero, exit
VirtToPhys i_xxETHERNET,s_xxETHERNET,i_xxETHERNET,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
390 mov r0, r5 ; Return the status
ldmfd sp!, {r2 - r5, pc} ; Restore registers and return
LTORG ; Place a literal pool here
;------------------------------------------------------------------------------
;
; FUNCTION:
; PhysicalToVirtual
;
; DESCRIPTION:
; This routine will return the virtual address of the specified physical
; address.
;
; INPUT PARAMETERS:
; r0 - Physical address of interest
; r1 - 1 (Cache/Buffered), 2 (Cache/Non-Buffered) or 0 (Non-Cached/Non-Buffered)
; r2 - Address of location in which to store resultant virtual address
; (pointer to pointer)
;
; RETURNS:
; r0 - 0 = Success, -1 = Failure
; [r2] - Virtual address of the specified physical address
;
; GLOBAL EFFECTS:
; None
;
; ASSUMPTIONS:
; None
;
; CALLS:
; None
;
; CALLED BY:
; This routine can be called by "C" code.
;
; PROTOTYPE:
; UINT PhysicalToVirtual(PVOID VA, BOOL Flag, PVOID PA);
;
;------------------------------------------------------------------------------
PhysicalToVirtual
stmfd sp!, {r1, r3 - r6, lr} ; Save registers
mov r6, r1 ; Save copy of flag
mov r1, r2 ; Save the pointer for return va
cmp r6, #01 ; Check for cached/buffered address desired
beq %F400 ; If not cached/buffered, check address range
PhysToVirt p_cbSDRAM,s_cbSDRAM,v_cbSDRAM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F490 ; If zero, exit
400
cmp r6, #02 ; Check for cached address desired
beq %F410 ; If not cached, check address range
PhysToVirt p_cxSDRAM,s_cxSDRAM,v_cxSDRAM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F490 ; If zero, exit
410
PhysToVirt i_xxSDRAM,s_xxSDRAM,i_xxSDRAM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F490 ; If zero, exit
PhysToVirt i_xxPCMCIA,s_xxPCMCIA,i_xxPCMCIA,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F490 ; If zero, exit
PhysToVirt i_xxProcessorReg,s_xxProcessorReg,i_xxProcessorReg,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F490 ; If zero, exit
PhysToVirt i_xxPlatformReg,s_xxPlatformReg,i_xxPlatformReg,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F490 ; If zero, exit
PhysToVirt p_xxBOOTROM,s_xxBOOTROM,v_xxBOOTROM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F490 ; If zero, exit
PhysToVirt p_xxALTROM,s_xxALTROM,v_xxALTROM,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
beq %F490 ; If zero, exit
PhysToVirt i_xxETHERNET,s_xxETHERNET,i_xxETHERNET,r0,r1,r2,r3,r4,r5
cmp r5, #0 ; Check result
490 mov r0, r5 ; Return the status
ldmfd sp!, {r1, r3 - r6, pc} ; Restore registers and return
;------------------------------------------------------------------------------
;
; FUNCTION:
; GetCpuVersion()
;
; DESCRIPTION:
; This routine is called by "C" to retrieve the CPU version.
;
; INPUT PARAMETERS:
; None.
;
; RETURNS:
; R0 - The CPU version information.
;
; GLOBAL EFFECTS:
; None.
;
; ASSUMPTIONS:
; None.
;
; CALLS:
; None.
;
; CALLED BY:
; "C" code.
;
; PROTOTYPE:
; UINT GetCpuVersion(VOID);
;
;------------------------------------------------------------------------------
GetCpuVersion
stmfd sp!, {lr} ; Save registers
bl XsGetProcessorVersion ; Get CPU ID
ldmfd sp!, {pc} ; Restore registers and return
;------------------------------------------------------------------------------
;
; FUNCTION:
; IsMMUEnabled()
;
; DESCRIPTION:
; This routine is called by "C" to determine if the MMU is enabled.
;
; INPUT PARAMETERS:
; None.
;
; RETURNS:
; R0 - zero if MMU not enabled, non-zero of MMU enabled.
;
; GLOBAL EFFECTS:
; None.
;
; ASSUMPTIONS:
; None.
;
; CALLS:
; None.
;
; CALLED BY:
; "C" code.
;
; PROTOTYPE:
; UINT IsMMUEnabled(VOID);
;
;------------------------------------------------------------------------------
IsMMUEnabled
stmfd sp!, {r1, lr} ; Save registers
getARMControl r0 ; Get co-processor 15 register 1
tst r0, #CONTROL_MMU ; Check MMU enable bit
bne %F500 ; If set, return MMU enabled
mov r0, #0 ; MMU not enabled
b %F510 ; Exit
500 mov r0, #1 ; MMU enabled
510
ldmfd sp!, {r1, pc} ; Restore registers and return
;------------------------------------------------------------------------------
;
; FUNCTION:
; IsICacheEnabled()
;
; DESCRIPTION:
; This routine is called by "C" to determine if the ICache is enabled.
;
; INPUT PARAMETERS:
; None.
;
; RETURNS:
; R0 - zero if ICache not enabled, non-zero of ICache enabled.
;
; GLOBAL EFFECTS:
; None.
;
; ASSUMPTIONS:
; None.
;
; CALLS:
; None.
;
; CALLED BY:
; "C" code.
;
; PROTOTYPE:
; UINT IsICacheEnabled(VOID);
;
;------------------------------------------------------------------------------
IsICacheEnabled
stmfd sp!, {r1, lr} ; Save registers
getARMControl r0 ; Get co-processor 15 register 1
tst r0, #CONTROL_ICACHE ; Check ICache enable bit
bne %F600 ; If set, return ICache enabled
mov r0, #0 ; ICache not enabled
b %F610 ; Exit
600 mov r0, #1 ; ICache enabled
610
ldmfd sp!, {r1, pc} ; Restore registers and return
;------------------------------------------------------------------------------
;
; FUNCTION:
; IsDCacheEnabled()
;
; DESCRIPTION:
; This routine is called by "C" to determine if the DCache is enabled.
;
; INPUT PARAMETERS:
; None.
;
; RETURNS:
; R0 - zero if DCache not enabled, non-zero of DCache enabled.
;
; GLOBAL EFFECTS:
; None.
;
; ASSUMPTIONS:
; None.
;
; CALLS:
; None.
;
; CALLED BY:
; "C" code.
;
; PROTOTYPE:
; UINT IsDCacheEnabled(VOID);
;
;------------------------------------------------------------------------------
IsDCacheEnabled
stmfd sp!, {r1, lr} ; Save registers
getARMControl r0 ; Get co-processor 15 register 1
tst r0, #CONTROL_DCACHE ; Check DCache enable bit
bne %F700 ; If set, return DCache enabled
mov r0, #0 ; DCache not enabled
b %F710 ; Exit
700 mov r0, #1 ; DCache enabled
710
ldmfd sp!, {r1, pc} ; Restore registers and return
;------------------------------------------------------------------------------
;
; FUNCTION:
; InitiateFCS
;
; DESCRIPTION:
; This subroutine checks r0 and r1 to see if turbo and/or fast bus mode, then
; initiates the frequency change sequence and restarts the memory controller
;
; INPUT PARAMETERS:
; int turbo: 1 - turbo mode; 0 - run mode.
; int fastBus: 1 - start fast bus mode; 0 - normal bus mode
;
; RETURNS:
; None.
;
; GLOBAL EFFECTS:
; Completes the process of changes the core frequency.
;
; ASSUMPTIONS:
; None.
;
; CALLS:
; None.
;
; CALLED BY:
; DVM device driver.
;
; PROTOTYPE:
; VOID InitiateFcs(int, int);
;
;------------------------------------------------------------------------------
;
InitiateFcs
; stmfd sp!, {r1, r2, lr} ; Save r1, r2 and link register on the stack
stmfd sp!, {r0, r1, r2, lr} ; Save r0, r1, r2 and link register on the stack
and r0, r0, #1 ; Isolate LSB for turbo mode
and r1, r1, #1 ; Isolate LSB for fast bus mode
mov r1, r1, LSL #3 ; Move to bit position #3
mrc p14, 0, r2, c6, c0, 0 ; get present status of CP14
orr r2, r2, r0 ; Update with value from user for turbo
orr r2, r2, r1 ; Update with value from user for fast bus
orr r2, r2, #2 ; Set the F bit
mcr p14, 0, r2, c6, c0, 0 ; initiate the frequency change sequence - Wheeeeeeeee!
;
; If the clock frequency is chaged, the MDREFR Register must be rewritten, even
; if it's the same value. This will result in a refresh being performed and the
; refresh counter being reset to the reset interval. (Section 13.10.3, pg 13-17 of EAS)
;
ldr r2, =xlli_MEMORY_CONFIG_BASE ; Get memory controller base address
ldr r1, [r2, #xlli_MDREFR_offset] ; Get the current state of MDREFR
str r1, [r2, #xlli_MDREFR_offset] ; Re-write this value
ldmfd sp!, {r0, r1, r2, pc} ; Restore r0, r1, r2 and return to caller
;
Undefined_Handler
;
; Capture the register set
;
stmfd sp!, {r0} ; Save registers
ldr r0, =regset
str r1, [r0, #4]
str r2, [r0, #8]
str r3, [r0, #12]
str r4, [r0, #16]
str r5, [r0, #20]
str r6, [r0, #24]
str r7, [r0, #28]
str r8, [r0, #32]
str r9, [r0, #36]
str r10, [r0, #40]
str r11, [r0, #44]
str r12, [r0, #48]
str r14, [r0, #56]
str r15, [r0, #60]
ldmfd sp!, {r0} ; Restore registers and return
;
; Store the remaining registers
;
ldr r1, =regset
str r0, [r1, #0]
str r13, [r1, #52]
mrs r2, CPSR ; get the processor status
str r2, [r1, #64]
;
; Display the LED error codes here
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