📄 main.s
字号:
i_xxSRAM, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxPlatformReg, i_xxPlatformReg, \
i_xxPlatformReg, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxProcessorReg, i_xxProcessorReg, \
i_xxProcessorReg, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxBOOTROM, v_xxBOOTROM, \
p_xxBOOTROM, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxALTROM, v_xxALTROM, \
p_xxALTROM, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxPCMCIA, i_xxPCMCIA, \
i_xxPCMCIA, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxETHERNET, i_xxETHERNET, \
i_xxETHERNET, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxIntSRAM, i_xxIntSRAM, \
i_xxIntSRAM, SECTION_x0c0b0, Level1tab
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25890FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
bl xlli_MMU_init ; Init the MMU
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x258A0FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
bl xlli_goVirtual ; Fire up the MMU
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x258B0FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
; NOTE: at this point, the system is in virtual address translation
; mode, and physical addresses are no longer valid!
bl xlli_icache_enable ; Enable I-Cache, D-Cache, BTB
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
; the above code was added here for porting XLLI
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
mov r0, #0x00000001 ; Display pattern: 0x00000001
setHexLED r0, r1
b %F10
LTORG ; Place a literal pool here
10
;
; We have completed the low-level initialization code with MMU enabled. We
; now have to relocate to RAM, setup the stack, initialize the Diagnostic
; Manager runtime environment and jump to the Diagnostic Manager
; initialization code.
IF RELOCATE_ROM = 1
;
; We have completed the low-level initialization code. We now must relocate
; to RAM, setup the stack, initialize the DM runtime environment and
; jump to the POST initialization code.
;
bl CopyROM
mov r2, #0x00000002 ; Display pattern: 0x00000002
setHexLED r2, r3
;
; Switch to RAM.
;
bl StartAtRAM
mov r2, pc
setHexLED r2, r3
ENDIF ; RELOCATE_ROM
ENDIF ;;;;DEBUG
;] ;hzh 上面的代码被屏蔽掉了/******************************************************************/
;/**************************************************************************************************/
;初始化堆栈
;/**************************************************************************************************/
; Get the top of the RAM we can use for stack space.
; 获得堆栈的地址空间
IF DEBUG=1
ldr r0, =STACK_LOCATION
ELSE
ldr r0, =0xa3ffcf00 ;hzh
ENDIF
mov r10, r0 ; Save the top of memory
;为各种异常分配堆栈空间.
;
; Enter SYS mode and set up the SYS stack pointer
;
mov r1, #CPSR_Mode_SYS:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter UND mode and set up the UND stack pointer
;
mov r1, #0x1b:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter ABT mode and set up the ABT stack pointer
;
mov r1, #0x17:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter FIQ mode and set up the FIQ stack pointer
;
mov r1, #CPSR_Mode_FIQ:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Enter IRQ mode and set up the IRQ stack pointer
;
mov r1, #CPSR_Mode_IRQ:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
sub r0, r0, #STACK_SIZE ; Calculate the next stack pointer
;
; Set up the SVC stack pointer last and return to SVC mode
;
mov r1, #CPSR_Mode_SVC:OR:CPSR_I_Bit:OR:CPSR_F_Bit ; No interrupts
msr cpsr_c, r1
mov sp, r0 ; Store the Stack pointer for SYS mode
;/*****************************************************************************************/
;将FLASH的CODE拷贝到SDRAM中（RO_BASE指定的地址）
;=============================================== added by hzh
;bl xlli_icache_enable ; Enable I-Cache, D-Cache, BTB
;don't enable cache, make it's safe for download and boot!
;bl LedFlash ;led flash test after xlli_icache_enable, hzh
IF :DEF: BOOTABLE ;
adr r0, MAIN
ldr r2, BaseOfROM
cmp r0, r2
ldreq r0, TopOfROM
beq InitRam
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7}
stmia r2!, {r4-r7}
cmp r2, r3
bcc %B0
sub r2, r2, r3
sub r0, r0, r2
;初始化SDRAM
InitRam
ldr r2, BaseOfBSS
ldr r3, BaseOfZero
0
cmp r2, r3
ldrcc r1, [r0], #4
strcc r1, [r2], #4
bcc %B0
mov r0, #0
ldr r3, EndOfBSS
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
;跳转到C的主函数Main中
ldr pc, =GotoMain
GotoMain
;mov r0, #3
;bl LedSet
;IF :DEF: BOOTABLE
ldr r0, EndOfBSS
;ELSE
;ldr r0,=|Image$$ZI$$Limit|
;
bl PlatformMain
b GotoMain
ENDIF
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|
;LedSet
; mov r0, r0, lsl #3
; and r0, r0, #(3<<3)
; ldr r2, =xlli_GPIOREGS_PHYSICAL_BASE
; str r0, [r2, #xlli_GPCR0_offset]
; eor r0, r0, #(3<<3)
; str r0, [r2, #xlli_GPSR0_offset]
; mov pc, lr
; 点灯函数，用来调试BOOTLOADER
;LED_FLASH_TM EQU 0x01000000
; EXPORT LedFlash
;LedFlash
; ldr r0, =xlli_GPIOREGS_PHYSICAL_BASE
; mov r1, #(1<<3)
; mov r2, #(1<<4)
;0
; str r1, [r0, #xlli_GPSR0_offset]
; str r2, [r0, #xlli_GPCR0_offset]
; mov r3, #LED_FLASH_TM
;1
; subs r3, r3, #1
; bne %B1
; str r2, [r0, #xlli_GPSR0_offset]
; str r1, [r0, #xlli_GPCR0_offset]
; mov r3, #LED_FLASH_TM
;2
; subs r3, r3, #1
; bne %B2
; b %B0
; mov pc, lr
; LTORG ; Place a literal pool here
;===============================================
mov r0, #0x00000003 ; Display pattern: 0x00000002
setHexLED r0, r1
ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
ldr r1, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base| ; Zero init base
cmp r0, r1 ; Check that they are different
beq %F30
mov r5, #0x00000004 ; Display pattern: 0x00000004
setHexLED r5, r6
20 cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc %B20
mov r5, #0x00000005 ; Display pattern: 0x00000005
setHexLED r5, r6
30 ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
mov r2, #0
40 cmp r3, r1 ; Zero init
strcc r2, [r3], #4
bcc %B40
mov r5, #0x00000006 ; Display pattern: 0x00000006
setHexLED r5, r6
;
; Debug - set all memory to known pattern
;
ldr r2, =0x55555555
50 cmp r3, r10 ; Mem init
strcc r2, [r3], #4
bcc %B50
mov r5, #0x00000007 ; Display pattern: 0x00000007
setHexLED r5, r6
ldr r5, =PlatformMain
setHexLED r5, r6
;
; Now jump the the Diangostic Manager initialization code:
; VOID PlatformMain(PVOID memTop);
;
ldr r0, =|Image$$ZI$$Limit| ; Top of zero init segment
bl PlatformMain
;
; In a real application we wouldn't normally expect to return, however
; in case we do the debug monitor swi is used to halt the application.
;
mov r0, #0x18 ; angel_SWIreason_ReportException
ldr r1, =0x20026 ; ADP_Stopped_ApplicationExit
swi 0x123456 ; Angel semihosting ARM SWI
LTORG ; Place a literal pool here
;------------------------------------------------------------------------------
;
; FUNCTION:
; CopyROM
;
; DESCRIPTION:
; This routine relocates the POST to SDRAM.
;
; INPUT PARAMETERS:
; None.
;
; RETURNS:
; None.
;
; GLOBAL EFFECTS:
; The contents of POST stored in Flash is copied to SDRAM.
;
; ASSUMPTIONS:
; The memory controller has been initialized.
;
; CALLS:
; None.
;
; CALLED BY:
; POST.
;
; PROTOTYPE:
; VOID CopyROM(VOID);
;
;------------------------------------------------------------------------------
;
; Copy the ROM image to RAM and prepare for remap
;
; WARNING: Don't add any instruction between the label CopyROM
; and the SUB instructions below. This code is attempting to calculate
; the delta offset of this routine to cover the case when DM is stored
; in high flash.
;
CopyROM
sub r0, pc, #8 ; Get the current program counter
ldr r1, =ROM_BASE ; Get the beginning of flash
sub r0, r0, r1 ; Calculate the current offset
ldr r1, =CopyROM ; Get the compile time offset
sub r4, r0, r1 ; Calculate the program offset
;
; Now setup the registers as follows:
; R1 = Destination Address
; R2 = Source Starting Address
; R3 = Source Ending Address
; R4 = Relative program offset in ROM
;
ldr r1, =RAM_BASE ; Destination Address
ldr r2, =ROM_BASE ; Source Starting Address
add r2, r2, r4 ; Take into account our program offset
; ldr r3, =ROM_SIZE ; Size of Source
ldr r3,=0x200000
add r3, r3, r2 ; Calculate Source Ending Address
;
; Copy Source to Destination
;
100 ldr r0,[r2],#4
str r0,[r1],#4
;
; Check for end of copy
;
cmp r2,r3
bls %B100
;
; Verify the copy, setup the registers as follows:
; R1 = Destination Address
; R2 = Source Starting Address
; R3 = Source Ending Address
; R4 = Relative program offset in ROM
;
ldr r1, =RAM_BASE ; Destination Address
ldr r2, =ROM_BASE ; Source Starting Address
add r2, r2, r4 ; Take into account our program offset
;
; Verify that source equals destination
;
200 ldr r0,[r2],#4
ldr r4,[r1],#4
cmp r0,r4
bne CopyFail
;
; Check for end if verify
;
cmp r2,r3
bls %B200
mov pc,lr
CopyFail
ldr r2, =0xFFFF0004 ; Display pattern: 0xFFFF0004
setHexLED r2, r3
210
ldr r1, =0xFFFF
maskHexLED r1, r2, r3
pauseMilliSecs #250, r1, r2, r3
ldr r1, =0
maskHexLED r1, r2, r3
pauseMilliSecs #500, r1, r2, r3
b %B210
;------------------------------------------------------------------------------
;
; FUNCTION:
; StartAtRAM
;
; DESCRIPTION:
; This routine determines the address in RAM we should jump to.
;
; INPUT PARAMETERS:
; None.
;
; RETURNS:
; None.
;
; GLOBAL EFFECTS:
; Once this routine is executed, we're running from RAM.
;
; ASSUMPTIONS:
; The POST has been copied from Flash to RAM.
;
; CALLS:
; None.
;
; CALLED BY:
; POST.
;
; PROTOTYPE:
; VOID StartAtRAM(VOID);
;
;------------------------------------------------------------------------------
;
; Jump to the same address in RAM. Nothing to do in particular
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