📄 main.s
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;------------------------------------------------------------------------------
;
; COPYRIGHT (C) 2000, 2001 Intel Corporation.
;
; This software as well as the software described in it is furnished under
; license and may only be used or copied in accordance with the terms of the
; license. The information in this file is furnished for informational use
; only, is subject to change without notice, and should not be construed as
; a commitment by Intel Corporation. Intel Corporation assumes no
; responsibility or liability for any errors or inaccuracies that may appear
; in this document or any software that may be provided in association with
; this document.
; Except as permitted by such license, no part of this document may be
; reproduced, stored in a retrieval system, or transmitted in any form or by
; any means without the express written consent of Intel Corporation.
;
; FILENAME: main.s
;
; PURPOSE: This file contains the platform dependent startup code. This is
; the first code to run in the system and is responsible for
; dispatching the platform dependent low-level initialization code
; to the POST initialization routine (PlatformMain()).
;
; LAST MODIFIED: $Modtime: $
;------------------------------------------------------------------------------
;/**--------------文件信息--------------------------------------------------------------------------------
;**文 件 名: main.s
;**创 建 人: hzh
;**最后修改日期: 2005-11-28
;**描 述: PXA270的启动文件，
;**
;********************************************************************************************************/
;为regset分配数据区域
;------------------------------------------------------------------------------
; DATA AREA
;------------------------------------------------------------------------------
;
AREA BlockData, DATA, READWRITE
regset DCD 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
;
;------------------------------------------------------------------------------
; CODE AREA
;------------------------------------------------------------------------------
;代码段开始
AREA Init, CODE, READONLY, ALIGN=5
;
; HEADER FILES
;
; GET target.mac ; Include low-level initialization code macros
; 包含一些目标的头文件
GET common.inc ; Common defs
GET platform.mac ; Include platform macros
GET ostInit.mac ; OST macros
GET cp15.mac ; cp15 macros
GET map.inc ; map data
GET main.mac ; Include the local macros
GET main.inc ; Include local definitions
GET regBase.inc ; register addresses
GET error.inc
;
; The following symbols control various features of the low-level
; initialization code.
;
IF :DEF: BOOTABLE ;hzh
RELOCATE_ROM EQU 1 ; Reloate to RAM
DEBUG EQU 0
ELSE
RELOCATE_ROM EQU 0
DEBUG EQU 1
ENDIF
;ENABLE_INTERRUPTS EQU 1 ; Enable processor interrupts
;RELOCATE_ROM EQU 1 ; Reloate to RAM
ENABLE_INTERRUPTS EQU 1 ; Enable processor interrupts
;USE_OPTIMAL_MEMORY EQU 1 ; Sets to use the TOPT function (Set in build file)
;
; References to external symbols
;
IMPORT |Image$$RO$$Base| ; Base of ROM code, hzh
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
IMPORT XsGetProcessorVersion ; CPU version
IMPORT PlatformMain ; "C" platform main entrypoint
IMPORT DumpProcessorRegisters ; Display the processor registers
;
; 声明外部函数
;
EXPORT MAIN
EXPORT VirtualToPhysical
EXPORT PhysicalToVirtual
EXPORT GetCpuVersion
EXPORT IsMMUEnabled
EXPORT IsICacheEnabled
EXPORT IsDCacheEnabled
EXPORT InitiateFcs
;
; Main entry point
;
; 程序入口点
MAIN
ENTRY
;
; Exception vectors
; 中断向量表
b Reset_Handler ; Must be PIC
ldr pc, =Undefined_Handler
ldr pc, =SWI_Handler
ldr pc, =Prefetch_Handler
ldr pc, =Abort_Handler
nop
ldr pc, =IRQ_Handler
ldr pc, =FIQ_Handler
;/*****************************************************************************
;** 函数名称: Reset_Handler
;** 功能描述: 复位异常的处理程序
;** 输 入: 无
;** 输 出 : 无
;** 全局变量: 无
;** 调用模块: 无
;** 作 者:
;** 日 期:
;**-------------------------------------------------------------------------------------------------------
;*****************************************************************************/
Reset_Handler
;
; Put the processor into SVC mode with interrupts disabled (IRQ and FIQ).
; 进入特权模式，并进制IRQ和FIQ中断
mrs r14,CPSR ; get the processor status
bic r14,r14,#CPSR_Mode_Mask
orr r14,r14,#(CPSR_Mode_SVC:OR:CPSR_Int_Mask)
msr cpsr_cf,r14 ; SVC 32 mode with interrupts disabled
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
; the following code was added here for porting XLLI
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
GET xlli_Mainstone_defs.inc ; Platform defs
GET regBase.inc
GET xlli_Bulverde_defs.inc ; Processor defs
GET xlli_LowLev_mac.mac ; xlli macros
GET map.inc ; Virtual map data
;声明在该.s文件中引用的程序，当然必须在BOOTABLE被定义的前提下
IMPORT xlli_read_SCR
IMPORT xlli_GPIO_init
IMPORT xlli_mem_init
IMPORT xlli_intr_init
IMPORT xlli_clks_init
IMPORT xlli_freq_change
IMPORT xlli_pwrmgr_init
IMPORT xlli_ost_init
IMPORT xlli_initPageTable
IMPORT xlli_MMU_init
IMPORT xlli_goVirtual
IMPORT xlli_icache_enable
IMPORT xlli_setClocks
IMPORT xlli_setBufImp
IMPORT xlli_mem_restart ; Restart memory controller
IMPORT xlli_mem_Tmax ; Sets maximum memory configuration values
IMPORT xlli_mem_Topt ; Sets optimal memory configuration values based on MemClk frequency
;need not read_SCR, so clear it, hzh,internal memory Register
;ldr r1, =xlli_SCR_data;将内部SRAM空间BANK3的地址0x5C03FFFC的值清零
;mov r0, #0
;str r0, [r1]
bl xlli_read_SCR ; Read the SCR and LCDCR virtual register data
;/*******************************************************************/
IF :DEF: BOOTABLE ;如果定义了BOOTABLE这个变量，则将该工程代码作为Flash中的启动代码
;调用GPIO初始化程序
bl xlli_GPIO_init ; Init the GPIO pins to xlli defaults
;bl LedFlash ;led flash test after xlli_GPIO_init, hzh，为调试
;/***************************************************************************************************************/
;SDRAM控制寄存器初始化
mov r3, #5 ; SDRAM Buffer impedance strength
bl xlli_setBufImp ; Set SDRAM buffer Impedance
bl xlli_mem_init ; Initialize the memory controller
;/*****************************************************************************************************/
;下面电源管理相关寄存器的初始化
;/*****************************************************************************************************/
;===hzh
MEM_BASE_PHYSICAL EQU (0xA3A00000) ; A000 0000 + 3A0 0000
SLEEP_SAVE_OFFSET EQU (0x2BA000)
SLEEP_SAVE_BYTES EQU (0x1000)
SLEEP_TYPE_OFFSET EQU (SLEEP_SAVE_BYTES-4)
RESET_LAUNCH_ADDR_OFFSET EQU (SLEEP_TYPE_OFFSET-4)
SLEEP_SAVE_PHYSICAL_BASE EQU (MEM_BASE_PHYSICAL + SLEEP_SAVE_OFFSET)
SLEEP_TYPE_PHYSICAL EQU (SLEEP_SAVE_PHYSICAL_BASE + SLEEP_TYPE_OFFSET)
RESET_LAUNCH_ADDR_PHYSICAL EQU (SLEEP_SAVE_PHYSICAL_BASE + RESET_LAUNCH_ADDR_OFFSET)
SLEEP_TYPE_STANDARD EQU 0
SLEEP_TYPE_SOFT_RESET EQU 1
; After some basic init, try to resume if sleep reset.
ldr r0, =xlli_PMRCREGS_PHYSICAL_BASE ; Get the Power Manager base address
ldr r10, [r0, #xlli_RCSR_offset]
ldr r0, [r0, #xlli_PSPR_offset] ; And the contents of the PSPR
mov r1, r10 ; Packed RCSR+PSSR
bl XllpPmValidateResumeFromSleep ; R0 .. R6 lost
cmp r0, #0 ; Zero return: OK to restore
bne ResetFailedRestore ; Maybe not even a sleep reset.
;; NOTE: GPIO reset and sleep-mediated soft reset require the
;; same handling. So sleep-based soft reset will return,
;; but #RCSR_GPIO_RESET will be forced in r10 just below.
ldr r3, =(SLEEP_TYPE_PHYSICAL)
ldr r1, [r3]
cmp r1, #SLEEP_TYPE_SOFT_RESET
bne Sleep_Reset_Not_SoftReset
; For soft reset, force same execution path as GPIO reset
; Also invalidate checksum and change sleep type at the same time.
mov r1, #SLEEP_TYPE_STANDARD
str r1, [r3]
ldr r3, =(SLEEP_SAVE_PHYSICAL_BASE) ; checksum always at sleep base addr
ldr r1, [r3] ; Get checksum
add r1, r1, #1 ; Change
str r1, [r3] ; Put bad checksum
; Get previously saved launch address
ldr r4, =(RESET_LAUNCH_ADDR_PHYSICAL); pointer
ldr r3, [r4] ; launch address
mov r1, r10 ; Contains soft reset indicators.
mov pc, r3
nop ; These NOPs are used to flush the Pipeline
nop
nop
nop
nop
nop
nop
nop
Sleep_Reset_Not_SoftReset
ldr r0, =xlli_PMRCREGS_PHYSICAL_BASE ; Get the Power Manager base address
ldr r0, [r0, #xlli_PSPR_offset] ; Phys. addr of save data
mov r1, r10 ; Packed RCSR+PSSR
b XllpPmGoToContextRestoration ; Never returns.
ResetFailedRestore
;===
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25800FFF ; Progress indicator data for hex display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
bl xlli_intr_init ; Initialize the interrupt controller
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25810FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
; bl xlli_clks_init ; Initialize the clocks manager
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25820FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
; determine if the board is running from the PC flash or the MB flash.
; if Mainboard, then don't use TOPT functions
ldr r1, =xlli_SCR_data ; r1 gets the address of the data
ldr r0, [r1] ; r0 gets the contents of the address
ands r0, r0, #0x80000000 ; see if bit 31 is set
bne %F2 ; if bit set, then mainboard
; IF :DEF: USE_OPTIMAL_MEMORY ; testing if we want to optimize memory
bl xlli_mem_Tmax
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25830FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
bl xlli_mem_restart
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x2583AFFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
2
; ENDIF
;bl LedFlash ;led flash test after xlli_mem_Tmax, hzh
;调用时钟函数
bl xlli_setClocks ; will poke CCCR so must do Frequency Change
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x2583BFFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
bl xlli_freq_change
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x2583CFFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
;bl LedFlash ;led flash test after xlli_freq_change, hzh
; determine if the board is running from the PC flash or the MB flash.
; if Mainboard, then don't use TOPT functions
ldr r1, =xlli_SCR_data ; r1 gets the address of the data
ldr r0, [r1] ; r0 gets the contents of the address
ands r0, r0, #0x80000000 ; see if bit 31 is set
bne %F3 ; if bit set, then mainboard
; IF :DEF: USE_OPTIMAL_MEMORY
bl xlli_mem_Topt
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x2583DFFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
bl xlli_mem_restart
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x2583EFFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
; ENDIF
3
;初始化电源管理寄存器
bl xlli_pwrmgr_init ; initialize the power manager
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25840FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
;初始化系统定时器
bl xlli_ost_init ; initialize the OS timers
;bl LedFlash ;led flash test after xlli_mem_Topt, hzh
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25850FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
;
; Find out what kind of reset this was
;
ldr r0, =PMRCREGS_PHYSICAL_BASE ; get base address of power mgr / reset control regs
ldr r7, [r0, #RCSR_OFFSET] ; get current value of the reset controller status register
mov r3, #xlli_RCSR_ALL ; extract the reset cause bits
and r7, r7, r3
str r3, [r0, #RCSR_OFFSET] ; clear the reset cause bits (they're sticky)
tst r7, #xlli_RCSR_HWR ; determine if this is hardware reset
bne %F33
tst r7, #xlli_RCSR_GPR ; determine if this is gpio reset
ldrne r1, =ERR_RESET_GPR
bne %F31
tst r7, #xlli_RCSR_WDR ; determine if this is watchdog reset
ldrne r1, =ERR_RESET_WDR
bne %F31
tst r7, #xlli_RCSR_SMR ; determine if this is sleep reset
ldrne r1, =ERR_RESET_NONE
bne %F31
; Determine if we have a valid address in PSPR.
ldr r0, =HWConfig_PHYSICAL_ADDR
ldr r0, [r0] ; fetch Hardware configuration data
tst r0, #1
beq %F33
mov pc, r0 ; address is valid, branch to it
31 ; we are not prepared to handle this situation
; issue error msg to hex LED and go into infinite loop
;下面这三行代码可以省掉
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25860FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
[ {FALSE} ;hzh, handle these as hard reset!
32 mov r1, r1
b %B32 ; Loop forever
] ;hzh
ENDIF ; BOOTABLE
;
; Continute with Hardware init
; NOTE: r7 should still contain the reset cause bits
33
;[ {FALSE} ;hzh
IF DEBUG=1
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25870FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
bl xlli_initPageTable ; Init memory map page table
ldr r1, =xlli_PLATFORM_REGISTERS
ldr r8, =0x25880FFF ; Progress indicator for HEX display
str r8, [r1, #xlli_PLATFORM_HEXLED_DATA_offset]
; Generate Level 1 page table entries
xlli_mapSECTIONS r1, r2, r3, r4, s_cbSDRAM, v_cbSDRAM, \
p_cbSDRAM, SECTION_x0c1b1, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxSDRAM, i_xxSDRAM, \
i_xxSDRAM, SECTION_x0c0b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_cxSDRAM, v_cxSDRAM, \
p_cxSDRAM, SECTION_x0c1b0, Level1tab
xlli_mapSECTIONS r1, r2, r3, r4, s_xxSRAM, i_xxSRAM, \
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