m6250_reg.cmm

QUALCOMM JNAND DRIVER

;****************************************************************************
;**           m6250_reg.cmm                                                **
;**           Call this script segment from any script to do an initial    **
;**           configuration of MSM6250 in preparation for a software load. **
;**                                                                        **
;**           Changes:                                                     **
;**           05-13-2003    Modified for MSM6250
;**           11-27-2002    Created                                        **
;****************************************************************************

; This .cmm file is a general-purpose initialization file for the MSM6250.
; The script configures some AHB peripheral registers, as well as commonly
; used GPIOs. 
; 
; In general, registers that need to be set up for the majority of verification
; work are configured below.  Registers with suitable default values are left
; as-is, unless it is difficult to verify that the default setting is actually working.
;
; Since many registers are not set up, (including clock configuration registers)
; this script is intended to be used after resetting the system. 

;--------------------------------------------------------------------------
; ARM clock controller registers
;--------------------------------------------------------------------------
; MICROPROCESSOR CLOCK CONFIGURATION
; After RESET, uP clock should default to TCXO/1. 
; Clocks are not initialized here since the default values should work
; properly. Cougar defaults to all clocks off, so turn them on. 

; MSM_CLK_ENA0
DATA.SET 0x84001400 %LONG 0x3FFFFFFF

; MSM_CLK_ENA1
DATA.SET 0x84001404 %LONG 0x0000000F

;--------------------------------------------------------------------------
; Decoder registers
;--------------------------------------------------------------------------
;--------------------------------------------------------------------------
;EBI1_CFG
;--------------------------------------------------------------------------

DATA.SET 0x600000A0 %word 0x0200 ; this is the power on default value

;EBI1_MPMC_STDY_SEL, configures static or dynamic memory on RAMCS2 and RAMCS3
DATA.SET 0x600000A8 %byte 0x00 ;static memory

;EBI1_PSRAM_CRE, controls the PSRAM CRE pin for synchronous Micron PSRAM
DATA.SET 0x600000AC %byte 0x01 ;no default listed in software interface

;EBI1_CS0_CFG0, configures timing and page size for CS0 - default value
DATA.SET 0x600000B0 %long 0x0033FC00 ; use the defaults for now

;EBI1_CS0_CFG1, configures timing and burst data
DATA.SET 0x600000B4 %byte 0x00 ; default is 0

;EBI1_CS1_CFG0
DATA.SET 0x600000B8 %long 0x0033FC00    ; same as CS0_CFG0 - default value

;EBI1_CS1_CFG1
DATA.SET 0x600000BC %byte 0x00 	        ;same as CS0_CFG1

;EBI1_CS2_CFG0
DATA.SET 0x600000C0 %long 0x0033FC00    ; same as CS0_CFG0 - default value

;EBI1_CS2_CFG1
DATA.SET 0x600000C4 %byte 0x00 		;same as CS0_CFG1

;EBI1_CS3_CFG0
DATA.SET 0x600000C8 %long 0x0033FC00    ;same as CS0_CFG0  - default value

;EBI1_CS3_CFG1
DATA.SET 0x600000CC %byte 0x00 		;same as CS0_CFG1


;EBI1_MEM_CTLR_SEL_CMD probably don't want to write to this register
;EBI1_MEM_CTLR_SEL_STATUS, returns which controller is used
;0 is the default state which equal XMEMC
;DATA.SET 0x600000D0 %byte 0x0;

;--------------------------------------------------------------------------
;EBI2_CFG
;--------------------------------------------------------------------------


;EBI2_CFG, set for EBI2_CS_N[2] is controlled by NAND flash controler
; and ARM priority
; memory range 0x20000000--0x27ffffff
DATA.SET 0x600000E0 %byte 0x02

;GP0_CFG0 corresponds to EBI2_CS0 
;memory range 0x28000000--0x2fffffff
DATA.SET 0x600000E4 %long 0x03111122 ;hopefully a good guess on timing
;GP0_CFG1, controls device size
DATA.SET 0x600000E8 %byte 0x00 ;ram is 16 bit device and user can write memory

;GP1_CFG0 corresponds to EBI2_CS1
;memory range 0x30000000--0x37ffffff
DATA.SET 0x600000EC %long 0x03111122 ;same as GP0_CFG0
;GP1_CFG1, same as GP0_CFG1
DATA.SET 0x600000F0 %byte 0x00

;RAM2_CFG0, same as GP0_CFG0 corresponds to EBI2_CS3
;memory range 0x40000000--0x47ffffff
DATA.SET 0x600000F4 %long 0x03111122
;RAM2_CFG1, same as GP0_CFG1
DATA.SET 0x600000F8 %byte 0x00

;ROM2_CFG0, same as GP0_CFG0 corresponds to EBI2_CS2
;memory range 0x38000000-0x37ffffff
DATA.SET 0x600000FC %long 0x03111122
;ROM2_CFG1, same as GP0_CFG1
DATA.SET 0x60000100 %byte 0x00

;LCD_CFG0 31:0, don't know a good value yet or if needed
DATA.SET 0x60000104 %long 0x77770807
;LCD_CFG1 24:0, controls lcd timing and type
DATA.SET 0x60000108 %long 0x0000000

;--------------------------------------------------------------------------
; Interface configuration registers
;--------------------------------------------------------------------------
; MSM_BRIDGE_CFG
; Not configured.  Use default value.
DATA.SET 0x60000080 %long 0x00000000 

; AUXMSM_BRIDGE_CFG 
; AUXMSM bridge access parameters control the hold cycles, setup cycles, and
; wait cycles for the AUXMSM-uP interface.  The register is uninitialized after
; power-up.  It is initialized to 0x0 here, to be the same as the default value
; for MSM_ACCESS_CFG.
DATA.SET 0x60000084 %LONG 0x00000000

; GPIO2_ACCESS_CFG 
; GPIO2 bridge access parameters control the hold cycles, setup cycles, and
; wait cycles for the GPIO2-uP interface.  The register is uninitialized after
; power-up.  It is initialized to 0x0 here, to be the same as the default value
; for MSM_ACCESS_CFG.
DATA.SET 0x60000088 %LONG 0

;MDSP_INTF_CFG, default state
DATA.SET 0x6000008C %byte 0x07 

; ADSP_INTF_CFG
; ADSP_INTF_CFG is a write-only register, and the power up value cannot be 
; verified easily.  To be safe, set the register to default values.
DATA.SET 0x60000090 %LONG 0x07


;--------------------------------------------------------------------------
; GPIO registers
;--------------------------------------------------------------------------
; There are several chip selects and address bits muxed behind
; MSM6250 GPIOs. These GPIOs are configured as shown below so they
; can be used for code download and debugging.
;
; GPIO     ALT FUNCTION                 GPIO_FUNC_SEL_X      bit in GPIO_FUNC_SEL_X
;                                              X            reg
; -------------------------------------------------------------------------------------
;  33      NAND2_FLASH_READY                   1              1
;  34      A2[20]                              1              2
;  35      XMEM2_CS_N[2]                       1              3
;  36      XMEM2_CS_N[3]                       1              4
;  37      LCD2_EN                             1              5
;  38      LCD2_CS_N                           1              6
;  67      SDRAM1_D[16]                        4              0
;  68      SDRAM1_D[17]                        4              1
;  69      SDRAM1_D[18]                        4              2
;  70	   SDRAM1_D[19]                        4              3
;  71	   SDRAM1_D[20]     	               4              4
;  72	   SDRAM1_D[21]                        4              5
;  73	   SDRAM1_D[22]     	               4              6 
;  74	   SDRAM1_D[23]     	               4              7
;  75	   SDRAM1_DQM[3]                       4              8
;  76	   XMEM1_CS_N[1]     	               4              9
;  77      XMEM1_CS_N[3] or SDRAM1_CS_n[1]     4              10
;  78      A[23]  or SDRAM1_DQM[2]             4              11
;  79      A[24]  or SDRAM1_A[0]               4              12
;  

; GPIO_FUNC_SEL_0    - no alternate function
DATA.SET 0x84000174 %LONG 0x00000000		

; GPIO_FUNC_SEL_1    - gpio[38:33] altrenate fct. see table above
DATA.SET 0x84000178 %LONG 0x0000007E

; GPIO_FUNC_SEL_4    - gpio[67:79] altrenate fct. see table above
DATA.SET 0x8400017C %LONG 0x00001FFF


; GPIO_ALT_FUNC_SEL  - default value
DATA.SET 0x84000180 %LONG 0x00000000