constants.cmm

来自「QUALCOMM JNAND DRIVER」· CMM 代码 · 共 407 行

;****************************************************************************
;**           Constants.CMM                                                **
;**           This script holds MSM6250's constants                        **
;**                                                                        **
;**                                                                        **
;**           Changes:                                                     **
;**           07-23-03   Added GPLL_CTL and GPIO_OE_0 register defines     ** 
;**           05-12-03   Changes for MSM6250                               **
;**           05-01-02   First version                                     **
;****************************************************************************
;


;
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;
;
; TARGET information settings
;
;
;
; Target -- intended to be booleans
global &TARGET_TYPE
&TARGET_TYPE="UNDEF" //MASTODON_SURF&6250

; Boot Mode -- indicates boot from NAND or boot from NOR -- SDRAM activated for NAND, Static RAM for NOR
global &BOOT_MODE
&BOOT_MODE="UNDEF" //NAND, NOR

global &SHADOW_MODE
&SHADOW_MODE=0

;Flag indicating if MPMC (ARM PL172) should be setup, put into self-refresh, etc.
global &SETUP_MPMC_SDRAM
&SETUP_MPMC_SDRAM=0

;Flag indicating if XMEMC (Qualcomm's mem ctrlr) should be setup.
global &SETUP_XMEMC
&SETUP_XMEMC=0

; SDRAM type (16-bit, 2x16-bit, 32-bit)
global &SDRAM_WIDTH
&SDRAM_WIDTH="16-bit" // safest config

; Microprocessor (ARM) clock rate, MHz
global &MCLK_RATE
&MCLK_RATE=19200000.

; Target's highest possible Micro CLK speed, MHz
global &TARGET_MAX_MCLK_RATE
&TARGET_MAX_MCLK_RATE=&MCLK_RATE // should be set from target config out of ROM

; Internal AHB bus clock rate, MHz
global &HCLK_RATE
&HCLK_RATE=19200000.

; Target's highest HCLK speed, MHz
global &TARGET_MAX_HCLK_RATE
&TARGET_MAX_HCLK_RATE=&HCLK_RATE // should be set from target config out of ROM

; timing margin for memory controller setup, nanoseconds
global &MEM_CTL_MARGIN_NS
&MEM_CTL_MARGIN_NS=100. // wildly high value, just for safety


; NAND block (erasable unit) size -- needed to autodetect the target settings
global &NAND_BLOCK_SIZE
&NAND_BLOCK_SIZE=0x4000  // 4000 is a 16kB block size)

;
;
; Load-safety feature variables
;
;
;
; the following registers indicate registers readable from the CPLD, indicating surf config
global &SURF_CONFIG_REGISTER0
&SURF_CONFIG_REGISTER0=0x30010000
global &SURF_CONFIG_REGISTER1
&SURF_CONFIG_REGISTER1=0x30010002
global &SURF_CONFIG_REGISTER2
&SURF_CONFIG_REGISTER2=0x30010004
global &SURF_CONFIG_REGISTER3
&SURF_CONFIG_REGISTER3=0x30010006


;
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;
;  MSM Registers and variables
;
;
;
; MSM ID register
global &HW_REVISION_NUMBER 
global &HW_REVISION_NUMBER_MSM6250
&HW_REVISION_NUMBER=0x84000104
;;--------------------------------------------------------------------------
;; TODO : Fill in this field after reviewing the HDD
;;--------------------------------------------------------------------------
&HW_REVISION_NUMBER_MSM6250=0

;;--------------------------------------------------------------------------
;; MSM6250 does not define this register. This register is also not used
;; in any of the cmm files
;;--------------------------------------------------------------------------
; CHIP_MODE register (gives mode pin values)
;global &CHIP_MODE
;&CHIP_MODE=0x80000758
;;--------------------------------------------------------------------------

; Register to control the GPLL
global &GPLL_CTL
&GPLL_CTL=0x8400130C
;FEATURE_SAMSUNG
global &CPLL_CTL
&CPLL_CTL=0x84001330
; Register to Enable clocks MSM_CLK_ENA0 and MSM_CLK_ENA1
global &MSM_CLK_ENA0
global &MSM_CLK_ENA1
&MSM_CLK_ENA0=0x84001400
&MSM_CLK_ENA1=0x84001404


; GPIO Function select registers
global &GPIO_FUNC_SEL0
global &GPIO_FUNC_SEL1
global &GPIO_FUNC_SEL4
&GPIO_FUNC_SEL0=0x84000174
&GPIO_FUNC_SEL1=0x84000178
&GPIO_FUNC_SEL4=0x8400017C

;  GPIO alternate function select register, for selecting GPIO functions
global &GPIO_ALT_FUNC_SEL
&GPIO_ALT_FUNC_SEL=0x84000180

; GPIO OE register
global &GPIO_OE_0
&GPIO_OE_0=0x84000150

;JKMIN
global &GPIO_OUT_0
&GPIO_OUT_0=0x8400015C

;
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;
; Memory Map variables
;
;
;
;  Chip Select Addresses
; These are stated as generic base addrs here because the boot mode choice swaps the
; addresses around for the different memories.
global &CS_EBI1_FIRST_BASE_ADDR
&CS_EBI1_FIRST_BASE_ADDR=0x00000000

global &CS_EBI1_SECOND_BASE_ADDR
&CS_EBI1_SECOND_BASE_ADDR=0x08000000

global &CS_EBI1_THIRD_BASE_ADDR
&CS_EBI1_THIRD_BASE_ADDR=0x10000000

global &CS_EBI1_FOURTH_BASE_ADDR
&CS_EBI1_FOURTH_BASE_ADDR=0x18000000

; EBI1 memory addresses -- these should be assigned base addresses after target
;  configuration is understood
global &EBI1_SDRAM_BASE_ADDR
global &EBI1_DATA_PSRAM_BASE_ADDR
global &EBI1_PSRAM_BASE_ADDR
global &EBI1_NOR_BASE_ADDR      // page, burst, or async NOR

; EBI2 addresses -- these don't move around based on configuration, so hard code them
global &EBI2_LCD_BASE_ADDR
&EBI2_LCD_BASE_ADDR=0x20000000

global &EBI2_NAND_FLASH_BASE_ADDR
&EBI2_NAND_FLASH_BASE_ADDR=0x28000000

global &EBI2_NOR_BASE_ADDR
&EBI2_NOR_BASE_ADDR=0x38000000

;
;
;
;  Memory interface and controller registers
;
;
;
;


; register to switch memory controllers
global &EBI1_MEM_CTLR_SEL_CMD
&EBI1_MEM_CTLR_SEL_CMD=0x600000D0

; register to read memory controllers switch -- 0 is XMEMC, 1 is MPMC active
global &EBI1_MEM_CTLR_SEL_STATUS &EBI1_MEM_CTLR_SEL_STATUS_XMEMC &EBI1_MEM_CTLR_SEL_STATUS_MPMC
&EBI1_MEM_CTLR_SEL_STATUS=0x600000D4
&EBI1_MEM_CTLR_SEL_STATUS_XMEMC=0x0
&EBI1_MEM_CTLR_SEL_STATUS_MPMC=0x1

;EBI1_PSRAM_CRE, sets the CRE pin when using PSRAM
global &EBI1_PSRAM_CRE
&EBI1_PSRAM_CRE=0x600000AC

; EBI1_CFG-- setups up debug clk enable, clk invert, and that SDRAM is present in the system
global &EBI1_CFG
&EBI1_CFG=0x600000A0

; selects dynamic or static memory for chip selects for CS2 and CS3
global &EBI1_MPMC_STDY_SEL
&EBI1_MPMC_STDY_SEL=0x600000A8

; EBI1_CSn_CFG0 registers configure the XMEMC for the different Chip selects
global &EBI1_CS0_CFG0 &EBI1_CS1_CFG0 &EBI1_CS2_CFG0 &EBI1_CS3_CFG0
&EBI1_CS0_CFG0=0x600000B0
&EBI1_CS1_CFG0=0x600000B8
&EBI1_CS2_CFG0=0x600000C0
&EBI1_CS3_CFG0=0x600000C8

; EBI1_CSn_CFG1 registers configure the XMEMC for the different Chip selects
global &EBI1_CS0_CFG1 &EBI1_CS1_CFG1 &EBI1_CS2_CFG1 &EBI1_CS3_CFG1
&EBI1_CS0_CFG1=0x600000B4
&EBI1_CS1_CFG1=0x600000BC
&EBI1_CS2_CFG1=0x600000C4
&EBI1_CS3_CFG1=0x600000CC

; EBI2_CFG-- setups up NAND Flash enable and ARM Priority
global &EBI2_CFG
&EBI2_CFG=0x600000E0

; GPn_CFG0, RAM2_CFG0, ROM2_CFG0 configure the EBI2 XMEMC for the different chip selects
global &GP0_CFG0 &GP1_CFG0 &RAM2_CFG0 &ROM2_CFG0
&GP0_CFG0=0x600000E4
&GP1_CFG0=0x600000EC
&RAM2_CFG0=0x600000F4
&ROM2_CFG0=0x600000FC

; GPn_CFG1, RAM2_CFG1, ROM2_CFG1 configure the EBI2 XMEMC for the different chip selects
global &GP0_CFG1 &GP1_CFG1 &RAM2_CFG1 &ROM2_CFG1
&GP0_CFG1=0x600000E8
&GP1_CFG1=0x600000F0
&RAM2_CFG1=0x600000F8
&ROM2_CFG1=0x60000100

; LCD_CFG0, LCD_CFG1 Configure the LCD characteristics
global &LCD_CFG0 &LCD_CFG1
&LCD_CFG0=0x60000104
&LCD_CFG1=0x60000108

; MSM_BRIDGE_CFG
global &MSM_BRIDGE_CFG
&MSM_BRIDGE_CFG=0x60000080

; AUXMSM_BRIDGE_CFG 
; AUXMSM bridge access parameters control the hold cycles, setup cycles, and
; wait cycles for the AUXMSM-uP interface.
global &AUXMSM_BRIDGE_CFG
&AUXMSM_BRIDGE_CFG=0x60000084

; GPIO2_ACCESS_CFG sets up the GPIO2 to uP bridge
global &GPIO2_ACCESS_CFG
&GPIO2_ACCESS_CFG=0x60000088

;MDSP_INTF_CFG, default state
global &MDSP_INTF_CFG
&MDSP_INTF_CFG=0x6000008C

; ADSP_INTF_CFG
global &ADSP_INTF_CFG
&ADSP_INTF_CFG=0x60000090

; NAND block registers
global &NAND_FLASH_CMD &NAND_FLASH_ADDR &NAND_FLASH_STATUS &NAND_BUFFER &NAND_BUFFER_END
&NAND_FLASH_CMD=0x64000300
&NAND_FLASH_ADDR=0x64000304
&NAND_FLASH_STATUS=0x64000308
&NAND_BUFFER=0x64000000
&NAND_BUFFER_END=&NAND_BUFFER+0x1FF


;
;
;
;

;
;
;  ARM PL172 MPMC (MultiPort Memory Controller) registers
;
;
; For documentation on the following, see ARM PL172 TRM (ARM DDI 0215A)
;
; ARM PL172 Memory controller
global &MPMC_BASE_ADDR
&MPMC_BASE_ADDR=0x63800000

global &MPMCControl
&MPMCControl=&MPMC_BASE_ADDR+0x0000

global &MPMCStatus
&MPMCStatus=&MPMC_BASE_ADDR+0x0004

global &MPMCConfig
&MPMCConfig=&MPMC_BASE_ADDR+0x0008

global &MPMCDynamicControl
&MPMCDynamicControl=&MPMC_BASE_ADDR+0x0020

global &MPMCDynamicRefresh
&MPMCDynamicRefresh=&MPMC_BASE_ADDR+0x0024

global &MPMCDynamictRP
&MPMCDynamictRP=&MPMC_BASE_ADDR+0x0030

global &MPMCDynamictRAS
&MPMCDynamictRAS=&MPMC_BASE_ADDR+0x0034

global &MPMCDynamictSREX
&MPMCDynamictSREX=&MPMC_BASE_ADDR+0x0038

global &MPMCDynamictAPR
&MPMCDynamictAPR=&MPMC_BASE_ADDR+0x003C

global &MPMCDynamictDAL
&MPMCDynamictDAL=&MPMC_BASE_ADDR+0x0040

global &MPMCDynamictWR
&MPMCDynamictWR=&MPMC_BASE_ADDR+0x0044

global &MPMCDynamictRC
&MPMCDynamictRC=&MPMC_BASE_ADDR+0x0048

global &MPMCDynamictRFC
&MPMCDynamictRFC=&MPMC_BASE_ADDR+0x004C

global &MPMCDynamictXSR
&MPMCDynamictXSR=&MPMC_BASE_ADDR+0x0050

global &MPMCDynamictRRD
&MPMCDynamictRRD=&MPMC_BASE_ADDR+0x0054

global &MPMCDynamictMRD
&MPMCDynamictMRD=&MPMC_BASE_ADDR+0x0058

global &MPMCDynamicConfig0
&MPMCDynamicConfig0=&MPMC_BASE_ADDR+0x0100

global &MPMCDynamicRasCas0
&MPMCDynamicRasCas0=&MPMC_BASE_ADDR+0x0104

global &MPMCDynamicConfig1
&MPMCDynamicConfig1=&MPMC_BASE_ADDR+0x0120

global &MPMCDynamicRasCas1
&MPMCDynamicRasCas1=&MPMC_BASE_ADDR+0x0124

global &MPMCDynamicConfig2
&MPMCDynamicConfig2=&MPMC_BASE_ADDR+0x0140

global &MPMCDynamicRasCas2
&MPMCDynamicRasCas2=&MPMC_BASE_ADDR+0x0144

global &MPMCDynamicConfig3
&MPMCDynamicConfig3=&MPMC_BASE_ADDR+0x0160

global &MPMCDynamicRasCas3
&MPMCDynamicRasCas3=&MPMC_BASE_ADDR+0x0164

global &MPMCStaticConfig0
&MPMCStaticConfig0=&MPMC_BASE_ADDR+0x0200

global &MPMCStaticConfig1
&MPMCStaticConfig1=&MPMC_BASE_ADDR+0x0220

global &MPMCStaticConfig2
&MPMCStaticConfig2=&MPMC_BASE_ADDR+0x0240

global &MPMCStaticConfig3
&MPMCStaticConfig3=&MPMC_BASE_ADDR+0x0260



;
;
;
;
; Physical constants
;
;
;
;
global &SECS_TO_NANOSECS
&SECS_TO_NANOSECS=1.0e9 // use this format else integer overflows occur

ENDDO