setupebi2.cmm
来自「QUALCOMM JNAND DRIVER」· CMM 代码 · 共 56 行
CMM
56 行
;****************************************************************************
;** SetupEBI2.CMM **
;** This script sets up MSM6250's EBI2 **
;** **
;** Changes: **
;** 05-12-03 MSM6250 changes **
;** 06-05-02 First version **
;****************************************************************************
;
; BEWARE that this script has different behavior based on the value in &HCLK_RATE
; -- timing values are calculated on the fly, based off HCLK_RATE
; setup EBI2_CFG, set for NAND flash enable and ARM priority
d.out &EBI2_CFG %LONG 0x02
;GPn_CFG0, RAM2_CFG0, ROM2_CFG0, configures timing
d.out &GP0_CFG0 %long 0x03111122
d.out &GP1_CFG0 %long 0x03111122
d.out &RAM2_CFG0 %long 0x03111122
d.out &ROM2_CFG0 %long 0x03111122
;EBI1_CSn_CFG1, configures bus sizing and write protect
d.out &GP0_CFG1 %byte 0x00 ;ram is 16 bit device and user can write memory
d.out &GP1_CFG1 %byte 0x00
d.out &RAM2_CFG1 %byte 0x00
d.out &ROM2_CFG1 %byte 0x00
; LCD setup
d.out &LCD_CFG0 %LONG 0x77770807
d.out &LCD_CFG1 %LONG 0x00
; MSM_BRIDGE_CFG
; Not configured. Use default value.
d.out &MSM_BRIDGE_CFG %LONG 0x00
; AUXMSM_BRIDGE_CFG
; AUXMSM bridge access parameters control the hold cycles, setup cycles, and
; wait cycles for the AUXMSM-uP interface. The register is uninitialized after
; power-up. It is initialized to 0x0 here, to be the same as the default value
; for MSM_ACCESS_CFG.
d.out &AUXMSM_BRIDGE_CFG %LONG 0x00
; Setup GPIO2 bridge to uP (setup, hold times)
;d.out &GPIO2_ACCESS_CFG %LONG 0x29111
d.out &GPIO2_ACCESS_CFG %LONG 0x0
;MDSP_INTF_CFG, default state
d.out &MDSP_INTF_CFG %byte 0x07
; ADSP_INTF_CFG
; ADSP_INTF_CFG is a write-only register, and the power up value cannot be
; verified easily. To be safe, set the register to default values.
d.out &ADSP_INTF_CFG %byte 0x07
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