📄 dm642main.c
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/********************************************************************/
/* Copyright 2004 by SEED Incorporated. */
/* All rights reserved. Property of SEED Incorporated. */
/* Restricted rights to use, duplicate or disclose this code are */
/* granted through contract. */
/* */
/********************************************************************/
#include <stdio.h>
#include <std.h>
#include <csl.h>
#include <csl_emifa.h>
#include <csl_irq.h>
#include <csl_chip.h>
#include "seeddm642.h"
#define SEEDDM642_SDRAM_BASE 0x80000000
#define SEEDDM642_SDRAM_BASE1 0x80010000
#define EMIFA_GCTL 0x01800000
#define EMIFA_CE1 0x01800004
#define EMIFA_CE0 0x01800008
#define EMIFA_CE2 0x01800010
#define EMIFA_CE3 0x01800014
#define EMIFA_SDRAMCTL 0x01800018
#define EMIFA_SDRAMTIM 0x0180001c
#define EMIFA_SDRAMEXT 0x01800020
#define EMIFA_CE1SECCTL 0x01800044
#define EMIFA_CE0SECCTL 0x01800048
#define EMIFA_CE2SECCTL 0x01800050
#define EMIFA_CE3SECCTL 0x01800054
/*SEEDDM642的emifa的设置结构*/
EMIFA_Config Seeddm642ConfigA ={
EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK) |
EMIFA_FMKS(GBLCTL, EK2HZ, CLK) |
EMIFA_FMKS(GBLCTL, EK2EN, ENABLE) |
EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS) |
EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE) |
EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ) |
EMIFA_FMKS(GBLCTL, EK1EN, ENABLE) |
EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE) |
EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE),
EMIFA_FMKS(CECTL, WRSETUP, DEFAULT) |
EMIFA_FMKS(CECTL, WRSTRB, DEFAULT) |
EMIFA_FMKS(CECTL, WRHLD, DEFAULT) |
EMIFA_FMKS(CECTL, RDSETUP, DEFAULT) |
EMIFA_FMKS(CECTL, TA, DEFAULT) |
EMIFA_FMKS(CECTL, RDSTRB, DEFAULT) |
EMIFA_FMKS(CECTL, MTYPE, SDRAM64) |
EMIFA_FMKS(CECTL, RDHLD, DEFAULT),
EMIFA_FMKS(CECTL, WRSETUP, OF(7)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(14)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(14)) |
EMIFA_FMKS(CECTL, MTYPE, ASYNC8) |
EMIFA_FMKS(CECTL, RDHLD, OF(1)),
EMIFA_FMKS(CECTL, WRSETUP, OF(2)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(10)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(10)) |
EMIFA_FMKS(CECTL, MTYPE, ASYNC32) |
EMIFA_FMKS(CECTL, RDHLD, OF(2)),
EMIFA_FMKS(CECTL, WRSETUP, OF(2)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(10)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(10)) |
EMIFA_FMKS(CECTL, MTYPE, SYNC32) |
EMIFA_FMKS(CECTL, RDHLD, OF(2)),
EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS) |
EMIFA_FMKS(SDCTL, SDRSZ, 12ROW) |
EMIFA_FMKS(SDCTL, SDCSZ, 8COL) |
EMIFA_FMKS(SDCTL, RFEN, ENABLE) |
EMIFA_FMKS(SDCTL, INIT, YES) |
EMIFA_FMKS(SDCTL, TRCD, OF(2)) |
EMIFA_FMKS(SDCTL, TRP, OF(2)) |
EMIFA_FMKS(SDCTL, TRC, OF(7)) |
EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
EMIFA_FMKS(SDTIM, XRFR, OF(0)) |
EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
EMIFA_FMKS(SDEXT, WR2RD, OF(1)) |
EMIFA_FMKS(SDEXT, WR2DEAC, OF(3)) |
EMIFA_FMKS(SDEXT, WR2WR, OF(1)) |
EMIFA_FMKS(SDEXT, R2WDQM, OF(3)) |
EMIFA_FMKS(SDEXT, RD2WR, OF(2)) |
EMIFA_FMKS(SDEXT, RD2DEAC, OF(3)) |
EMIFA_FMKS(SDEXT, RD2RD, OF(1)) |
EMIFA_FMKS(SDEXT, THZP, OF(0)) |
EMIFA_FMKS(SDEXT, TWR, OF(1)) |
EMIFA_FMKS(SDEXT, TRRD, OF(1)) |
EMIFA_FMKS(SDEXT, TRAS, OF(5)) |
EMIFA_FMKS(SDEXT, TCL, OF(1)),
/* EMIFA_FMKS(CECTL, WRSETUP, OF(7)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(14)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(14)) |
EMIFA_FMKS(CECTL, MTYPE, ASYNC8) |
EMIFA_FMKS(CECTL, RDHLD, OF(1)),
EMIFA_FMKS(CECTL, WRSETUP, OF(2)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(10)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(10)) |
EMIFA_FMKS(CECTL, MTYPE, ASYNC32) |
EMIFA_FMKS(CECTL, RDHLD, OF(2)),
EMIFA_FMKS(CECTL, WRSETUP, OF(2)) |
EMIFA_FMKS(CECTL, WRSTRB, OF(10)) |
EMIFA_FMKS(CECTL, WRHLD, OF(2)) |
EMIFA_FMKS(CECTL, RDSETUP, OF(2)) |
EMIFA_FMKS(CECTL, TA, OF(2)) |
EMIFA_FMKS(CECTL, RDSTRB, OF(10)) |
EMIFA_FMKS(CECTL, MTYPE, SYNC32) |
EMIFA_FMKS(CECTL, RDHLD, OF(2)),
EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS) |
EMIFA_FMKS(SDCTL, SDRSZ, 12ROW) |
EMIFA_FMKS(SDCTL, SDCSZ, 8COL) |
EMIFA_FMKS(SDCTL, RFEN, ENABLE) |
EMIFA_FMKS(SDCTL, INIT, YES) |
EMIFA_FMKS(SDCTL, TRCD, OF(1)) |
EMIFA_FMKS(SDCTL, TRP, OF(1)) |
EMIFA_FMKS(SDCTL, TRC, OF(5)) |
EMIFA_FMKS(SDCTL, SLFRFR, DISABLE),
EMIFA_FMKS(SDTIM, XRFR, OF(0)) |
EMIFA_FMKS(SDTIM, PERIOD, OF(2075)),
EMIFA_FMKS(SDEXT, WR2RD, OF(1)) |
EMIFA_FMKS(SDEXT, WR2DEAC, OF(3)) |
EMIFA_FMKS(SDEXT, WR2WR, OF(1)) |
EMIFA_FMKS(SDEXT, R2WDQM, OF(3)) |
EMIFA_FMKS(SDEXT, RD2WR, OF(2)) |
EMIFA_FMKS(SDEXT, RD2DEAC, OF(3)) |
EMIFA_FMKS(SDEXT, RD2RD, OF(1)) |
EMIFA_FMKS(SDEXT, THZP, OF(2)) |
EMIFA_FMKS(SDEXT, TWR, OF(2)) |
EMIFA_FMKS(SDEXT, TRRD, OF(0)) |
EMIFA_FMKS(SDEXT, TRAS, OF(6)) |
EMIFA_FMKS(SDEXT, TCL, OF(1)), */
EMIFA_CESEC_DEFAULT,
EMIFA_CESEC_DEFAULT,
EMIFA_CESEC_DEFAULT,
EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2) |
EMIFA_FMKS(CESEC, RENEN, READ) |
EMIFA_FMKS(CESEC, CEEXT, ACTIVE) |
EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE) |
EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE)
};
extern far void vectors();
/*test the sdram*/
void main()
{
Uint32 i;
Uint8 check = 0;
Uint32 block = 0;
/* Return lower 8 bits of register */
/*-------------------------------------------------------*/
/* perform all initializations */
/*-------------------------------------------------------*/
/*Initialise CSL，初始化CSL库*/
CSL_init();
/*----------------------------------------------------------*/
/*EMIFA的初始化，将CE0设为SDRAM空间，CE1设为异步空间
注，DM642支持的是EMIFA，而非EMIF*/
// EMIFA_config(&Seeddm642ConfigA);
/* EMIFA */
*(int *)EMIFA_GCTL = 0x00052078;//0x00012078;
*(int *)EMIFA_CE0 = 0xffffffd3;//0xffffffdf; /* CE0 SDRAM */
*(int *)EMIFA_CE1 = 0x73a28e01; /* CE1 Flash + CPLD */
*(int *)EMIFA_CE2 = 0x22a28a22; /* CE2 Daughtercard 32-bit async */
*(int *)EMIFA_CE3 = 0xffffff03;//0x22a28a42; /* CE3 Daughtercard 32-bit sync */
*(int *)EMIFA_SDRAMCTL = 0x57115000; /* SDRAM control */
*(int *)EMIFA_SDRAMTIM = 0x0000081b; /* SDRAM timing (refresh) */
*(int *)EMIFA_SDRAMEXT = 0x000002a8;//0x001faeab; /* SDRAM extended control */
*(int *)EMIFA_CE0SECCTL= 0x00000002; /* CE0 Secondary Control Reg. */
*(int *)EMIFA_CE1SECCTL= 0x00000002; /* CE1 Secondary Control Reg. */
*(int *)EMIFA_CE2SECCTL= 0x00000002; /* CE2 Secondary Control Reg. */
*(int *)EMIFA_CE3SECCTL= 0x00000002;//0x00000073; /* CE3 Secondary Control Reg. */
/*----------------------------------------------------------*/
/*中断向量表的初始化*/
//Point to the IRQ vector table
IRQ_setVecs(vectors);
IRQ_nmiEnable();
IRQ_globalEnable();
IRQ_map(IRQ_EVT_VINT1, 11);
IRQ_map(IRQ_EVT_VINT0, 12);
IRQ_reset(IRQ_EVT_VINT1);
IRQ_reset(IRQ_EVT_VINT1);
/*----------------------------------------------------------*/
// *(Uint8 *)(0x90000100) = 85;
/*sdram的测试,sdram的地址从0x8000 0000开始，长度为32M字节*/
//写头256个字节
for(block = 0;block <0x100000;block++)
{
for(i = 0;i<0x10;i++)
{
*((Uint8 *)(SEEDDM642_SDRAM_BASE + i+(block<<4))) = i;
}
block++;
for(i = 0;i<0x10;i++)
{
*((Uint8 *)(SEEDDM642_SDRAM_BASE + i+(block<<4))) = i;
}
/*read and check*/
block--;
for(i = 0;i<0x10;i++)
{
check = *((Uint8 *)(SEEDDM642_SDRAM_BASE + i+(block<<4)));
if(check != i)
{
for(;;)
{
// printf("the error address is 0x%x\n",SEEDDM642_SDRAM_BASE + i + (block<<8));
break;
}
}
}
block++;
for(i = 0;i<0x10;i++)
{
check = *((Uint8 *)(SEEDDM642_SDRAM_BASE + i+(block<<4)));
if(check != i)
{
for(;;)
{
// printf("the error address is 0x%x\n",SEEDDM642_SDRAM_BASE + i+(block<<8));
break;
}
}
}
}
printf("the SDRAM test done!\n");
/*测试完成*/
for(;;){}
}
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